PPC: [Atomics] Make Atomics.exchange a builtin using TF

src/ppc/assembler-ppc.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 580 matching lines @@
 #define DECLARE_PPC_X_INSTRUCTIONS_F_FORM(name, instr_name, instr_value)    \
   inline void name(const Register src1, const Register src2,                \
                    const CRegister cr = cr7, const RCBit rc = LeaveRC) {    \
     x_form(instr_name, cr, src1, src2, rc);                                 \
   }                                                                         \
   inline void name##w(const Register src1, const Register src2,             \
                       const CRegister cr = cr7, const RCBit rc = LeaveRC) { \
     x_form(instr_name, cr.code() * B2, src1.code(), src2.code(), LeaveRC);  \
   }
 
+#define DECLARE_PPC_X_INSTRUCTIONS_EH_S_FORM(name, instr_name, instr_value) \
+  inline void name(const Register dst, const MemOperand& src) {             \
+    x_form(instr_name, src.ra(), dst, src.rb(), SetEH);                     \
+  }
+#define DECLARE_PPC_X_INSTRUCTIONS_EH_L_FORM(name, instr_name, instr_value) \
+  inline void name(const Register dst, const MemOperand& src) {             \
+    DCHECK(!src.ra_.is(r0));                                                \
+    x_form(instr_name, src.ra(), dst, src.rb(), SetEH);                     \
+  }
+
   inline void x_form(Instr instr, int f1, int f2, int f3, int rc) {
     emit(instr | f1 * B21 | f2 * B16 | f3 * B11 | rc);
   }
   inline void x_form(Instr instr, Register rs, Register ra, Register rb,
                      RCBit rc) {
     emit(instr | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 | rc);
   }
+  inline void x_form(Instr instr, Register ra, Register rs, Register rb,
+                     EHBit eh = SetEH) {
+    emit(instr | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 | eh);
+  }
   inline void x_form(Instr instr, CRegister cr, Register s1, Register s2,
                      RCBit rc) {
 #if V8_TARGET_ARCH_PPC64
     int L = 1;
 #else
     int L = 0;
 #endif
     emit(instr | cr.code() * B23 | L * B21 | s1.code() * B16 |
          s2.code() * B11 | rc);
   }
 
   PPC_X_OPCODE_A_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_A_FORM)
   PPC_X_OPCODE_B_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_B_FORM)
   PPC_X_OPCODE_C_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_C_FORM)
   PPC_X_OPCODE_D_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_D_FORM)
   PPC_X_OPCODE_E_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_E_FORM)
   PPC_X_OPCODE_F_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_F_FORM)
+  PPC_X_OPCODE_EH_S_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_EH_S_FORM)
+  PPC_X_OPCODE_EH_L_FORM_LIST(DECLARE_PPC_X_INSTRUCTIONS_EH_L_FORM)
 
   inline void notx(Register dst, Register src, RCBit rc = LeaveRC) {
     nor(dst, src, src, rc);
   }
   inline void lwax(Register rt, const MemOperand& src) {
 #if V8_TARGET_ARCH_PPC64
     Register ra = src.ra();
     Register rb = src.rb();
     DCHECK(!ra.is(r0));
     x_form(LWAX, rt, ra, rb, LeaveRC);
 #else
     lwzx(rt, src);
 #endif
   }
   inline void extsw(Register rs, Register ra, RCBit rc = LeaveRC) {
 #if V8_TARGET_ARCH_PPC64
     emit(EXT2 | EXTSW | ra.code() * B21 | rs.code() * B16 | rc);
 #else
     // nop on 32-bit
     DCHECK(rs.is(ra) && rc == LeaveRC);
 #endif
   }
 
 #undef DECLARE_PPC_X_INSTRUCTIONS_A_FORM
 #undef DECLARE_PPC_X_INSTRUCTIONS_B_FORM
 #undef DECLARE_PPC_X_INSTRUCTIONS_C_FORM
 #undef DECLARE_PPC_X_INSTRUCTIONS_D_FORM
 #undef DECLARE_PPC_X_INSTRUCTIONS_E_FORM
 #undef DECLARE_PPC_X_INSTRUCTIONS_F_FORM
+#undef DECLARE_PPC_X_INSTRUCTIONS_EH_S_FORM
+#undef DECLARE_PPC_X_INSTRUCTIONS_EH_L_FORM
 
 #define DECLARE_PPC_XX3_INSTRUCTIONS(name, instr_name, instr_value)  \
   inline void name(const DoubleRegister rt, const DoubleRegister ra, \
                    const DoubleRegister rb) {                        \
     xx3_form(instr_name, rt, ra, rb);                                \
   }
 
   inline void xx3_form(Instr instr, DoubleRegister t, DoubleRegister a,
                        DoubleRegister b) {
     int AX = ((a.code() & 0x20) >> 5) & 0x1;
@@ skipping 307 matching lines @@
   void lbz(Register dst, const MemOperand& src);
   void lhz(Register dst, const MemOperand& src);
   void lha(Register dst, const MemOperand& src);
   void lwz(Register dst, const MemOperand& src);
   void lwzu(Register dst, const MemOperand& src);
   void lwa(Register dst, const MemOperand& src);
   void stb(Register dst, const MemOperand& src);
   void sth(Register dst, const MemOperand& src);
   void stw(Register dst, const MemOperand& src);
   void stwu(Register dst, const MemOperand& src);
-
   void neg(Register rt, Register ra, OEBit o = LeaveOE, RCBit c = LeaveRC);
 
 #if V8_TARGET_ARCH_PPC64
   void ld(Register rd, const MemOperand& src);
   void ldu(Register rd, const MemOperand& src);
   void std(Register rs, const MemOperand& src);
   void stdu(Register rs, const MemOperand& src);
   void rldic(Register dst, Register src, int sh, int mb, RCBit r = LeaveRC);
   void rldicl(Register dst, Register src, int sh, int mb, RCBit r = LeaveRC);
   void rldcl(Register ra, Register rs, Register rb, int mb, RCBit r = LeaveRC);
@@ skipping 545 matching lines @@
   PatchingAssembler(IsolateData isolate_data, byte* address, int instructions);
   ~PatchingAssembler();
 
   void FlushICache(Isolate* isolate);
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_PPC_ASSEMBLER_PPC_H_