MIPS[64]: Support for some SIMD operations

src/compiler/mips64/instruction-selector-mips64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 123 matching lines @@
 };
 
 
 static void VisitRR(InstructionSelector* selector, ArchOpcode opcode,
                     Node* node) {
   Mips64OperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)));
 }
 
+static void VisitRRI(InstructionSelector* selector, ArchOpcode opcode,
+                     Node* node) {
+  Mips64OperandGenerator g(selector);
+  int32_t imm = OpParameter<int32_t>(node);
+  selector->Emit(opcode, g.DefineAsRegister(node),
+                 g.UseRegister(node->InputAt(0)), g.UseImmediate(imm));
+}
+
+static void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode,
+                      Node* node) {
+  Mips64OperandGenerator g(selector);
+  int32_t imm = OpParameter<int32_t>(node);
+  selector->Emit(opcode, g.DefineAsRegister(node),
+                 g.UseRegister(node->InputAt(0)), g.UseImmediate(imm),
+                 g.UseRegister(node->InputAt(1)));
+}
 
 static void VisitRRR(InstructionSelector* selector, ArchOpcode opcode,
                      Node* node) {
   Mips64OperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)),
                  g.UseRegister(node->InputAt(1)));
 }
 
 
@@ skipping 2481 matching lines @@
          addr_reg, g.TempImmediate(0), g.UseRegisterOrImmediateZero(value));
   }
 }
 
 void InstructionSelector::VisitAtomicExchange(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitInt32x4Splat(Node* node) {
+  VisitRR(this, kMips64Int32x4Splat, node);
+}
+
+void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
+  VisitRRI(this, kMips64Int32x4ExtractLane, node);
+}
+
+void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) {
+  VisitRRIR(this, kMips64Int32x4ReplaceLane, node);
+}
+
+void InstructionSelector::VisitInt32x4Add(Node* node) {
+  VisitRRR(this, kMips64Int32x4Add, node);
+}
+
+void InstructionSelector::VisitInt32x4Sub(Node* node) {
+  VisitRRR(this, kMips64Int32x4Sub, node);
+}
+
+void InstructionSelector::VisitSimd128Zero(Node* node) {
+  Mips64OperandGenerator g(this);
+  Emit(kMips64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x4Zero(Node* node) {
+  Mips64OperandGenerator g(this);
+  Emit(kMips64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x8Zero(Node* node) {
+  Mips64OperandGenerator g(this);
+  Emit(kMips64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x16Zero(Node* node) {
+  Mips64OperandGenerator g(this);
+  Emit(kMips64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags;
   return flags | MachineOperatorBuilder::kWord32Ctz |
          MachineOperatorBuilder::kWord64Ctz |
          MachineOperatorBuilder::kWord32Popcnt |
          MachineOperatorBuilder::kWord64Popcnt |
          MachineOperatorBuilder::kWord32ShiftIsSafe |
          MachineOperatorBuilder::kInt32DivIsSafe |
@@ skipping 19 matching lines @@
   } else {
     DCHECK(kArchVariant == kMips64r2);
     return MachineOperatorBuilder::AlignmentRequirements::
         NoUnalignedAccessSupport();
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8