MIPS: Move ldc1/sdc1 to macro-assembler.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 1272 matching lines @@
            IsMipsArchVariant(kLoongson));
     mfc1(scratch, fd);
     Usw(scratch, rs);
   }
 }
 
 void MacroAssembler::Uldc1(FPURegister fd, const MemOperand& rs,
                            Register scratch) {
   DCHECK(!scratch.is(at));
   if (IsMipsArchVariant(kMips32r6)) {
-    ldc1(fd, rs);
+    Ldc1(fd, rs);
   } else {
     DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r1) ||
            IsMipsArchVariant(kLoongson));
     Ulw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset));
     mtc1(scratch, fd);
     Ulw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset));
     Mthc1(scratch, fd);
   }
 }
 
 void MacroAssembler::Usdc1(FPURegister fd, const MemOperand& rs,
                            Register scratch) {
   DCHECK(!scratch.is(at));
   if (IsMipsArchVariant(kMips32r6)) {
-    sdc1(fd, rs);
+    Sdc1(fd, rs);
   } else {
     DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r1) ||
            IsMipsArchVariant(kLoongson));
     mfc1(scratch, fd);
     Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset));
     Mfhc1(scratch, fd);
     Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset));
   }
 }
 
+void MacroAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
+  // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
+  // load to two 32-bit loads.
+  if (IsFp32Mode()) {  // fp32 mode.
+    if (is_int16(src.offset()) && is_int16(src.offset() + kIntSize)) {
+      lwc1(fd, MemOperand(src.rm(), src.offset() + Register::kMantissaOffset));
+      FPURegister nextfpreg;
+      nextfpreg.setcode(fd.code() + 1);
+      lwc1(nextfpreg,
+           MemOperand(src.rm(), src.offset() + Register::kExponentOffset));
+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      int32_t off16 = LoadUpperOffsetForTwoMemoryAccesses(src);
+      lwc1(fd, MemOperand(at, off16 + Register::kMantissaOffset));
+      FPURegister nextfpreg;
+      nextfpreg.setcode(fd.code() + 1);
+      lwc1(nextfpreg, MemOperand(at, off16 + Register::kExponentOffset));
+    }
+  } else {
+    DCHECK(IsFp64Mode() || IsFpxxMode());
+    // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
+    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+    if (is_int16(src.offset()) && is_int16(src.offset() + kIntSize)) {
+      lwc1(fd, MemOperand(src.rm(), src.offset() + Register::kMantissaOffset));
+      lw(at, MemOperand(src.rm(), src.offset() + Register::kExponentOffset));
+      mthc1(at, fd);
+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      int32_t off16 = LoadUpperOffsetForTwoMemoryAccesses(src);
+      lwc1(fd, MemOperand(at, off16 + Register::kMantissaOffset));
+      lw(at, MemOperand(at, off16 + Register::kExponentOffset));
+      mthc1(at, fd);
+    }
+  }
+}
+
+void MacroAssembler::Sdc1(FPURegister fd, const MemOperand& src) {
+  // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
+  // store to two 32-bit stores.
+  DCHECK(!src.rm().is(at));
+  DCHECK(!src.rm().is(t8));
+  if (IsFp32Mode()) {  // fp32 mode.
+    if (is_int16(src.offset()) && is_int16(src.offset() + kIntSize)) {
+      swc1(fd, MemOperand(src.rm(), src.offset() + Register::kMantissaOffset));
+      FPURegister nextfpreg;
+      nextfpreg.setcode(fd.code() + 1);
+      swc1(nextfpreg,
+           MemOperand(src.rm(), src.offset() + Register::kExponentOffset));
+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      int32_t off16 = LoadUpperOffsetForTwoMemoryAccesses(src);
+      swc1(fd, MemOperand(at, off16 + Register::kMantissaOffset));
+      FPURegister nextfpreg;
+      nextfpreg.setcode(fd.code() + 1);
+      swc1(nextfpreg, MemOperand(at, off16 + Register::kExponentOffset));
+    }
+  } else {
+    DCHECK(IsFp64Mode() || IsFpxxMode());
+    // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
+    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+    if (is_int16(src.offset()) && is_int16(src.offset() + kIntSize)) {
+      swc1(fd, MemOperand(src.rm(), src.offset() + Register::kMantissaOffset));
+      mfhc1(at, fd);
+      sw(at, MemOperand(src.rm(), src.offset() + Register::kExponentOffset));
+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      int32_t off16 = LoadUpperOffsetForTwoMemoryAccesses(src);
+      swc1(fd, MemOperand(at, off16 + Register::kMantissaOffset));
+      mfhc1(t8, fd);
+      sw(t8, MemOperand(at, off16 + Register::kExponentOffset));
+    }
+  }
+}
 
 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) {
   li(dst, Operand(value), mode);
 }
 
 
 void MacroAssembler::li(Register rd, Operand j, LiFlags mode) {
   DCHECK(!j.is_reg());
   BlockTrampolinePoolScope block_trampoline_pool(this);
   if (!MustUseReg(j.rmode_) && mode == OPTIMIZE_SIZE) {
@@ skipping 75 matching lines @@
 
 
 void MacroAssembler::MultiPushFPU(RegList regs) {
   int16_t num_to_push = NumberOfBitsSet(regs);
   int16_t stack_offset = num_to_push * kDoubleSize;
 
   Subu(sp, sp, Operand(stack_offset));
   for (int16_t i = kNumRegisters - 1; i >= 0; i--) {
     if ((regs & (1 << i)) != 0) {
       stack_offset -= kDoubleSize;
-      sdc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
+      Sdc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
     }
   }
 }
 
 
 void MacroAssembler::MultiPushReversedFPU(RegList regs) {
   int16_t num_to_push = NumberOfBitsSet(regs);
   int16_t stack_offset = num_to_push * kDoubleSize;
 
   Subu(sp, sp, Operand(stack_offset));
   for (int16_t i = 0; i < kNumRegisters; i++) {
     if ((regs & (1 << i)) != 0) {
       stack_offset -= kDoubleSize;
-      sdc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
+      Sdc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
     }
   }
 }
 
 
 void MacroAssembler::MultiPopFPU(RegList regs) {
   int16_t stack_offset = 0;
 
   for (int16_t i = 0; i < kNumRegisters; i++) {
     if ((regs & (1 << i)) != 0) {
-      ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
+      Ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
       stack_offset += kDoubleSize;
     }
   }
   addiu(sp, sp, stack_offset);
 }
 
 
 void MacroAssembler::MultiPopReversedFPU(RegList regs) {
   int16_t stack_offset = 0;
 
   for (int16_t i = kNumRegisters - 1; i >= 0; i--) {
     if ((regs & (1 << i)) != 0) {
-      ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
+      Ldc1(FPURegister::from_code(i), MemOperand(sp, stack_offset));
       stack_offset += kDoubleSize;
     }
   }
   addiu(sp, sp, stack_offset);
 }
 
 void MacroAssembler::AddPair(Register dst_low, Register dst_high,
                              Register left_low, Register left_high,
                              Register right_low, Register right_high) {
   Label no_overflow;
@@ skipping 1018 matching lines @@
 
 void MacroAssembler::TruncateDoubleToI(Register result,
                                        DoubleRegister double_input) {
   Label done;
 
   TryInlineTruncateDoubleToI(result, double_input, &done);
 
   // If we fell through then inline version didn't succeed - call stub instead.
   push(ra);
   Subu(sp, sp, Operand(kDoubleSize));  // Put input on stack.
-  sdc1(double_input, MemOperand(sp, 0));
+  Sdc1(double_input, MemOperand(sp, 0));
 
   DoubleToIStub stub(isolate(), sp, result, 0, true, true);
   CallStub(&stub);
 
   Addu(sp, sp, Operand(kDoubleSize));
   pop(ra);
 
   bind(&done);
 }
 
 
 void MacroAssembler::TruncateHeapNumberToI(Register result, Register object) {
   Label done;
   DoubleRegister double_scratch = f12;
   DCHECK(!result.is(object));
 
-  ldc1(double_scratch,
+  Ldc1(double_scratch,
        MemOperand(object, HeapNumber::kValueOffset - kHeapObjectTag));
   TryInlineTruncateDoubleToI(result, double_scratch, &done);
 
   // If we fell through then inline version didn't succeed - call stub instead.
   push(ra);
   DoubleToIStub stub(isolate(),
                      object,
                      result,
                      HeapNumber::kValueOffset - kHeapObjectTag,
                      true,
@@ skipping 1712 matching lines @@
 }
 
 
 void MacroAssembler::AllocateHeapNumberWithValue(Register result,
                                                  FPURegister value,
                                                  Register scratch1,
                                                  Register scratch2,
                                                  Label* gc_required) {
   LoadRoot(t8, Heap::kHeapNumberMapRootIndex);
   AllocateHeapNumber(result, scratch1, scratch2, t8, gc_required);
-  sdc1(value, FieldMemOperand(result, HeapNumber::kValueOffset));
+  Sdc1(value, FieldMemOperand(result, HeapNumber::kValueOffset));
 }
 
 
 void MacroAssembler::AllocateJSValue(Register result, Register constructor,
                                      Register value, Register scratch1,
                                      Register scratch2, Label* gc_required) {
   DCHECK(!result.is(constructor));
   DCHECK(!result.is(scratch1));
   DCHECK(!result.is(scratch2));
   DCHECK(!result.is(value));
@@ skipping 531 matching lines @@
   if ((flags & AVOID_NANS_AND_INFINITIES) != 0) {
     // If exponent is all ones the number is either a NaN or +/-Infinity.
     Register exponent = scratch1;
     Register mask_reg = scratch2;
     lw(exponent, FieldMemOperand(object, HeapNumber::kExponentOffset));
     li(mask_reg, HeapNumber::kExponentMask);
 
     And(exponent, exponent, mask_reg);
     Branch(not_number, eq, exponent, Operand(mask_reg));
   }
-  ldc1(result, FieldMemOperand(object, HeapNumber::kValueOffset));
+  Ldc1(result, FieldMemOperand(object, HeapNumber::kValueOffset));
   bind(&done);
 }
 
 
 void MacroAssembler::SmiToDoubleFPURegister(Register smi,
                                             FPURegister value,
                                             Register scratch1) {
   sra(scratch1, smi, kSmiTagSize);
   mtc1(scratch1, value);
   cvt_d_w(value, value);
@@ skipping 606 matching lines @@
     DCHECK(kDoubleSize == frame_alignment);
     if (frame_alignment > 0) {
       DCHECK(base::bits::IsPowerOfTwo32(frame_alignment));
       And(sp, sp, Operand(-frame_alignment));  // Align stack.
     }
     int space = FPURegister::kMaxNumRegisters * kDoubleSize;
     Subu(sp, sp, Operand(space));
     // Remember: we only need to save every 2nd double FPU value.
     for (int i = 0; i < FPURegister::kMaxNumRegisters; i+=2) {
       FPURegister reg = FPURegister::from_code(i);
-      sdc1(reg, MemOperand(sp, i * kDoubleSize));
+      Sdc1(reg, MemOperand(sp, i * kDoubleSize));
     }
   }
 
   // Reserve place for the return address, stack space and an optional slot
   // (used by the DirectCEntryStub to hold the return value if a struct is
   // returned) and align the frame preparing for calling the runtime function.
   DCHECK(stack_space >= 0);
   Subu(sp, sp, Operand((stack_space + 2) * kPointerSize));
   if (frame_alignment > 0) {
     DCHECK(base::bits::IsPowerOfTwo32(frame_alignment));
     And(sp, sp, Operand(-frame_alignment));  // Align stack.
   }
 
   // Set the exit frame sp value to point just before the return address
   // location.
   addiu(at, sp, kPointerSize);
   sw(at, MemOperand(fp, ExitFrameConstants::kSPOffset));
 }
 
 
 void MacroAssembler::LeaveExitFrame(bool save_doubles, Register argument_count,
                                     bool restore_context, bool do_return,
                                     bool argument_count_is_length) {
   // Optionally restore all double registers.
   if (save_doubles) {
     // Remember: we only need to restore every 2nd double FPU value.
     lw(t8, MemOperand(fp, ExitFrameConstants::kSPOffset));
     for (int i = 0; i < FPURegister::kMaxNumRegisters; i+=2) {
       FPURegister reg = FPURegister::from_code(i);
-      ldc1(reg, MemOperand(t8, i * kDoubleSize + kPointerSize));
+      Ldc1(reg, MemOperand(t8, i * kDoubleSize + kPointerSize));
     }
   }
 
   // Clear top frame.
   li(t8, Operand(ExternalReference(Isolate::kCEntryFPAddress, isolate())));
   sw(zero_reg, MemOperand(t8));
 
   // Restore current context from top and clear it in debug mode.
   if (restore_context) {
     li(t8, Operand(ExternalReference(Isolate::kContextAddress, isolate())));
@@ skipping 1008 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS