[ia32] Supplement shift instructions for SIMD

src/ia32/assembler-ia32.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1043 matching lines @@
   void movsd(const Operand& dst, XMMRegister src);
 
 
   void movss(XMMRegister dst, const Operand& src);
   void movss(const Operand& dst, XMMRegister src);
   void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
   void extractps(Register dst, XMMRegister src, byte imm8);
 
   void ptest(XMMRegister dst, XMMRegister src);
 
+  void psllw(XMMRegister reg, int8_t shift);
   void pslld(XMMRegister reg, int8_t shift);
+  void psrlw(XMMRegister reg, int8_t shift);
   void psrld(XMMRegister reg, int8_t shift);
+  void psraw(XMMRegister reg, int8_t shift);
+  void psrad(XMMRegister reg, int8_t shift);
   void psllq(XMMRegister reg, int8_t shift);
   void psllq(XMMRegister dst, XMMRegister src);
   void psrlq(XMMRegister reg, int8_t shift);
   void psrlq(XMMRegister dst, XMMRegister src);
   void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
   void pextrd(Register dst, XMMRegister src, int8_t offset) {
     pextrd(Operand(dst), src, offset);
   }
   void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
   void pinsrw(XMMRegister dst, Register src, int8_t offset) {
@@ skipping 223 matching lines @@
     vss(0x5f, dst, src1, src2);
   }
   void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
     vminss(dst, src1, Operand(src2));
   }
   void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
     vss(0x5d, dst, src1, src2);
   }
   void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
 
+  void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8);
+  void vpslld(XMMRegister dst, XMMRegister src, int8_t imm8);
+  void vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8);
+  void vpsrld(XMMRegister dst, XMMRegister src, int8_t imm8);
+  void vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8);
+  void vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8);
+
   // BMI instruction
   void andn(Register dst, Register src1, Register src2) {
     andn(dst, src1, Operand(src2));
   }
   void andn(Register dst, Register src1, const Operand& src2) {
     bmi1(0xf2, dst, src1, src2);
   }
   void bextr(Register dst, Register src1, Register src2) {
     bextr(dst, Operand(src1), src2);
   }
@@ skipping 325 matching lines @@
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_IA32_ASSEMBLER_IA32_H_