[ia32] Add some SSE2, SSE4 instructions and AVX version for SIMD

src/ia32/sse-instr.h

Index: src/ia32/sse-instr.h
diff --git a/src/ia32/sse-instr.h b/src/ia32/sse-instr.h
index 87175bd9bd519cee755433191f27620473575579..1d893155a69557529e8f4d894a75866f08a4ab2f 100644
--- a/src/ia32/sse-instr.h
+++ b/src/ia32/sse-instr.h
@@ -6,7 +6,50 @@
 #define V8_SSE_INSTR_H_
 
 #define SSE2_INSTRUCTION_LIST(V) \
+  V(paddb, 66, 0F, FC)           \
+  V(paddw, 66, 0F, FD)           \
   V(paddd, 66, 0F, FE)           \
-  V(psubd, 66, 0F, FA)
+  V(paddsb, 66, 0F, EC)          \
+  V(paddsw, 66, 0F, ED)          \
+  V(paddusb, 66, 0F, DC)         \
+  V(paddusw, 66, 0F, DD)         \
+  V(pand, 66, 0F, DB)            \
+  V(pcmpeqb, 66, 0F, 74)         \
+  V(pcmpeqw, 66, 0F, 75)         \
+  V(pcmpeqd, 66, 0F, 76)         \
+  V(pcmpgtb, 66, 0F, 64)         \
+  V(pcmpgtw, 66, 0F, 65)         \
+  V(pcmpgtd, 66, 0F, 66)         \
+  V(pmaxsw, 66, 0F, EE)          \
+  V(pmaxub, 66, 0F, DE)          \
+  V(pminsw, 66, 0F, EA)          \
+  V(pminub, 66, 0F, DA)          \
+  V(pmullw, 66, 0F, D5)          \
+  V(por, 66, 0F, EB)             \
+  V(psllw, 66, 0F, F1)           \
+  V(pslld, 66, 0F, F2)           \
+  V(psraw, 66, 0F, E1)           \
+  V(psrad, 66, 0F, E2)           \
+  V(psrlw, 66, 0F, D1)           \
+  V(psrld, 66, 0F, D2)           \
+  V(psubb, 66, 0F, F8)           \
+  V(psubw, 66, 0F, F9)           \
+  V(psubd, 66, 0F, FA)           \
+  V(psubsb, 66, 0F, E8)          \
+  V(psubsw, 66, 0F, E9)          \
+  V(psubusb, 66, 0F, D8)         \
+  V(psubusw, 66, 0F, D9)         \
+  V(pxor, 66, 0F, EF)
+
+#define SSE4_INSTRUCTION_LIST(V) \
+  V(pminsb, 66, 0F, 38, 38)      \
+  V(pminsd, 66, 0F, 38, 39)      \
+  V(pminuw, 66, 0F, 38, 3A)      \
+  V(pminud, 66, 0F, 38, 3B)      \
+  V(pmaxsb, 66, 0F, 38, 3C)      \
+  V(pmaxsd, 66, 0F, 38, 3D)      \
+  V(pmaxuw, 66, 0F, 38, 3E)      \
+  V(pmaxud, 66, 0F, 38, 3F)      \
+  V(pmulld, 66, 0F, 38, 40)
 
 #endif  // V8_SSE_INSTR_H_