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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2013 } | 2013 } |
2014 | 2014 |
2015 | 2015 |
2016 void Assembler::stop(const char* msg, uint32_t code) { | 2016 void Assembler::stop(const char* msg, uint32_t code) { |
2017 DCHECK(code > kMaxWatchpointCode); | 2017 DCHECK(code > kMaxWatchpointCode); |
2018 DCHECK(code <= kMaxStopCode); | 2018 DCHECK(code <= kMaxStopCode); |
2019 #if V8_HOST_ARCH_MIPS | 2019 #if V8_HOST_ARCH_MIPS |
2020 break_(0x54321); | 2020 break_(0x54321); |
2021 #else // V8_HOST_ARCH_MIPS | 2021 #else // V8_HOST_ARCH_MIPS |
2022 BlockTrampolinePoolFor(2); | 2022 BlockTrampolinePoolFor(2); |
2023 // The Simulator will handle the stop instruction and get the message address. | |
2024 // On MIPS stop() is just a special kind of break_(). | |
2025 break_(code, true); | 2023 break_(code, true); |
2026 // Do not embed the message string address! We used to do this, but that | |
2027 // made snapshots created from position-independent executable builds | |
2028 // non-deterministic. | |
2029 // TODO(yangguo): remove this field entirely. | |
2030 nop(); | |
2031 #endif | 2024 #endif |
2032 } | 2025 } |
2033 | 2026 |
2034 | 2027 |
2035 void Assembler::tge(Register rs, Register rt, uint16_t code) { | 2028 void Assembler::tge(Register rs, Register rt, uint16_t code) { |
2036 DCHECK(is_uint10(code)); | 2029 DCHECK(is_uint10(code)); |
2037 Instr instr = SPECIAL | TGE | rs.code() << kRsShift | 2030 Instr instr = SPECIAL | TGE | rs.code() << kRsShift |
2038 | rt.code() << kRtShift | code << 6; | 2031 | rt.code() << kRtShift | code << 6; |
2039 emit(instr); | 2032 emit(instr); |
2040 } | 2033 } |
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3277 | 3270 |
3278 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 3271 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
3279 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); | 3272 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); |
3280 } | 3273 } |
3281 } | 3274 } |
3282 | 3275 |
3283 } // namespace internal | 3276 } // namespace internal |
3284 } // namespace v8 | 3277 } // namespace v8 |
3285 | 3278 |
3286 #endif // V8_TARGET_ARCH_MIPS | 3279 #endif // V8_TARGET_ARCH_MIPS |
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