s390: implement atomic exchange on TF

src/s390/simulator-s390.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_S390
 
@@ skipping 824 matching lines @@
   EvalTable[SLDA] = &Simulator::Evaluate_SLDA;
   EvalTable[STM] = &Simulator::Evaluate_STM;
   EvalTable[TM] = &Simulator::Evaluate_TM;
   EvalTable[MVI] = &Simulator::Evaluate_MVI;
   EvalTable[TS] = &Simulator::Evaluate_TS;
   EvalTable[NI] = &Simulator::Evaluate_NI;
   EvalTable[CLI] = &Simulator::Evaluate_CLI;
   EvalTable[OI] = &Simulator::Evaluate_OI;
   EvalTable[XI] = &Simulator::Evaluate_XI;
   EvalTable[LM] = &Simulator::Evaluate_LM;
+  EvalTable[CS] = &Simulator::Evaluate_CS;
   EvalTable[MVCLE] = &Simulator::Evaluate_MVCLE;
   EvalTable[CLCLE] = &Simulator::Evaluate_CLCLE;
   EvalTable[MC] = &Simulator::Evaluate_MC;
   EvalTable[CDS] = &Simulator::Evaluate_CDS;
   EvalTable[STCM] = &Simulator::Evaluate_STCM;
   EvalTable[ICM] = &Simulator::Evaluate_ICM;
   EvalTable[BPRP] = &Simulator::Evaluate_BPRP;
   EvalTable[BPP] = &Simulator::Evaluate_BPP;
   EvalTable[TRTR] = &Simulator::Evaluate_TRTR;
   EvalTable[MVN] = &Simulator::Evaluate_MVN;
@@ skipping 5584 matching lines @@
     selection_mask = (static_cast<uint64_t>(1) << width) - 1;
   } else {
     selection_mask = static_cast<uint64_t>(static_cast<int64_t>(-1));
   }
   selection_mask = selection_mask << (63 - end_bit);
 
   uint64_t selected_val = rotated_val & selection_mask;
 
   if (!zero_remaining) {
     // Merged the unselected bits from the original value
-    selected_val = (src_val & ~selection_mask) | selected_val;
+    selected_val = (get_register(r1) & ~selection_mask) | selected_val;
   }
 
   // Condition code is set by treating result as 64-bit signed int
   SetS390ConditionCode<int64_t>(selected_val, 0);
   set_register(r1, selected_val);
   return length;
 }
 
 EVALUATE(AHIK) {
   DCHECK_OPCODE(AHIK);
@@ skipping 1344 matching lines @@
     return length;  // Done!
   }
 
   // Now we know selected bits mixed zeros and ones
   // Test if the leftmost bit is zero or one
 #if defined(__GNUC__)
   int leadingZeros = __builtin_clz(mask);
   mask = 0x80000000u >> leadingZeros;
   if (mask & r1_val) {
     // leftmost bit is one
-    condition_reg_ = 0x4;
+    condition_reg_ = 0x2;
   } else {
     // leftmost bit is zero
-    condition_reg_ = 0x2;
+    condition_reg_ = 0x4;
   }
   return length;  // Done!
 #else
   for (int i = 15; i >= 0; i--) {
     if (mask & (1 << i)) {
       if (r1_val & (1 << i)) {
         // leftmost bit is one
         condition_reg_ = 0x2;
       } else {
         // leftmost bit is zero
@@ skipping 2664 matching lines @@
   DCHECK_OPCODE(LLCR);
   DECODE_RRE_INSTRUCTION(r1, r2);
   uint32_t r2_val = get_low_register<uint32_t>(r2);
   r2_val <<= 24;
   r2_val >>= 24;
   set_low_register(r1, r2_val);
   return length;
 }
 
 EVALUATE(LLHR) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LLHR);
+  DECODE_RRE_INSTRUCTION(r1, r2);
+  uint32_t r2_val = get_low_register<uint32_t>(r2);
+  r2_val <<= 16;
+  r2_val >>= 16;
+  set_low_register(r1, r2_val);
+  return length;
 }
 
 EVALUATE(MLR) {
   DCHECK_OPCODE(MLR);
   DECODE_RRE_INSTRUCTION(r1, r2);
   DCHECK(r1 % 2 == 0);
 
   uint32_t r1_val = get_low_register<uint32_t>(r1 + 1);
   uint32_t r2_val = get_low_register<uint32_t>(r2);
   uint64_t product =
@@ skipping 1457 matching lines @@
   int64_t b2_val = (b2 == 0) ? 0 : get_register(b2);
   int shiftBits = (b2_val + d2) & 0x3F;
   // unsigned
   uint64_t r3_val = get_register(r3);
   uint64_t alu_out = 0;
   alu_out = r3_val << shiftBits;
   set_register(r1, alu_out);
   return length;
 }
 
+EVALUATE(CS) {
+  DCHECK_OPCODE(CS);
+  DECODE_RS_A_INSTRUCTION(r1, r3, rb, d2);
+  int32_t offset = d2;
+  int64_t rb_val = (rb == 0) ? 0 : get_register(rb);
+  intptr_t target_addr = static_cast<intptr_t>(rb_val) + offset;
+
+  int32_t r1_val = get_low_register<int32_t>(r1);
+  int32_t r3_val = get_low_register<int32_t>(r3);
+
+  DCHECK((target_addr & 0x3) == 0);
+  bool is_success = __atomic_compare_exchange_n(
+      reinterpret_cast<int32_t*>(target_addr), &r1_val, r3_val, true,
+      __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+  if (!is_success) {
+    set_low_register(r1, r1_val);
+    condition_reg_ = 0x4;
+  } else {
+    condition_reg_ = 0x8;
+  }
+  return length;
+}
+
 EVALUATE(CSY) {
+  DCHECK_OPCODE(CSY);
+  DECODE_RSY_A_INSTRUCTION(r1, r3, b2, d2);
+  int32_t offset = d2;
+  int64_t b2_val = (b2 == 0) ? 0 : get_register(b2);
+  intptr_t target_addr = static_cast<intptr_t>(b2_val) + offset;
+
+  int32_t r1_val = get_low_register<int32_t>(r1);
+  int32_t r3_val = get_low_register<int32_t>(r3);
+
+  DCHECK((target_addr & 0x3) == 0);
+  bool is_success = __atomic_compare_exchange_n(
+      reinterpret_cast<int32_t*>(target_addr), &r1_val, r3_val, true,
+      __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+  if (!is_success) {
+    set_low_register(r1, r1_val);
+    condition_reg_ = 0x4;
+  } else {
+    condition_reg_ = 0x8;
+  }
+  return length;
+}
+
+EVALUATE(CSG) {
   UNIMPLEMENTED();
   USE(instr);
   return 0;
 }
 
 EVALUATE(RLLG) {
   DCHECK_OPCODE(RLLG);
   // For SLLG/SRLG, the 64-bit third operand is shifted the number
   // of bits specified by the second-operand address, and the result is
   // placed at the first-operand location. Except for when the R1 and R3
@@ skipping 925 matching lines @@
   return 0;
 }
 
 #undef EVALUATE
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 #endif  // V8_TARGET_ARCH_S390