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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1797 // 32-bit Load Multiple - long displacement (20-bits signed) | 1797 // 32-bit Load Multiple - long displacement (20-bits signed) |
1798 void Assembler::lmy(Register r1, Register r2, const MemOperand& src) { | 1798 void Assembler::lmy(Register r1, Register r2, const MemOperand& src) { |
1799 rsy_form(LMY, r1, r2, src.rb(), src.offset()); | 1799 rsy_form(LMY, r1, r2, src.rb(), src.offset()); |
1800 } | 1800 } |
1801 | 1801 |
1802 // 64-bit Load Multiple - long displacement (20-bits signed) | 1802 // 64-bit Load Multiple - long displacement (20-bits signed) |
1803 void Assembler::lmg(Register r1, Register r2, const MemOperand& src) { | 1803 void Assembler::lmg(Register r1, Register r2, const MemOperand& src) { |
1804 rsy_form(LMG, r1, r2, src.rb(), src.offset()); | 1804 rsy_form(LMG, r1, r2, src.rb(), src.offset()); |
1805 } | 1805 } |
1806 | 1806 |
| 1807 // 32-bit Compare and Swap |
| 1808 void Assembler::cs(Register r1, Register r2, const MemOperand& src) { |
| 1809 rs_form(CS, r1, r2, src.rb(), src.offset()); |
| 1810 } |
| 1811 |
| 1812 // 32-bit Compare and Swap |
| 1813 void Assembler::csy(Register r1, Register r2, const MemOperand& src) { |
| 1814 rsy_form(CSY, r1, r2, src.rb(), src.offset()); |
| 1815 } |
| 1816 |
| 1817 // 64-bit Compare and Swap |
| 1818 void Assembler::csg(Register r1, Register r2, const MemOperand& src) { |
| 1819 rsy_form(CSG, r1, r2, src.rb(), src.offset()); |
| 1820 } |
| 1821 |
1807 // Move integer (32) | 1822 // Move integer (32) |
1808 void Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) { | 1823 void Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) { |
1809 sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); | 1824 sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); |
1810 } | 1825 } |
1811 | 1826 |
1812 // Move integer (64) | 1827 // Move integer (64) |
1813 void Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) { | 1828 void Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) { |
1814 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); | 1829 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); |
1815 } | 1830 } |
1816 | 1831 |
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2146 SKIP_ICACHE_FLUSH); | 2161 SKIP_ICACHE_FLUSH); |
2147 } | 2162 } |
2148 | 2163 |
2149 reloc_info_writer.Write(&rinfo); | 2164 reloc_info_writer.Write(&rinfo); |
2150 } | 2165 } |
2151 } | 2166 } |
2152 | 2167 |
2153 } // namespace internal | 2168 } // namespace internal |
2154 } // namespace v8 | 2169 } // namespace v8 |
2155 #endif // V8_TARGET_ARCH_S390 | 2170 #endif // V8_TARGET_ARCH_S390 |
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