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Side by Side Diff: runtime/vm/instructions_arm64.h

Issue 274043003: Adds debugger patching to arm64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // Classes that describe assembly patterns as used by inline caches. 4 // Classes that describe assembly patterns as used by inline caches.
5 5
6 #ifndef VM_INSTRUCTIONS_ARM64_H_ 6 #ifndef VM_INSTRUCTIONS_ARM64_H_
7 #define VM_INSTRUCTIONS_ARM64_H_ 7 #define VM_INSTRUCTIONS_ARM64_H_
8 8
9 #ifndef VM_INSTRUCTIONS_H_ 9 #ifndef VM_INSTRUCTIONS_H_
10 #error Do not include instructions_arm64.h directly; use instructions.h instead. 10 #error Do not include instructions_arm64.h directly; use instructions.h instead.
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37 intptr_t* value); 37 intptr_t* value);
38 38
39 // Decodes a load sequence ending at 'end' (the last instruction of the 39 // Decodes a load sequence ending at 'end' (the last instruction of the
40 // load sequence is the instruction before the one at end). Returns the 40 // load sequence is the instruction before the one at end). Returns the
41 // address of the first instruction in the sequence. Returns the register 41 // address of the first instruction in the sequence. Returns the register
42 // being loaded and the index in the pool being read from in the output 42 // being loaded and the index in the pool being read from in the output
43 // parameters 'reg' and 'index' respectively. 43 // parameters 'reg' and 'index' respectively.
44 static uword DecodeLoadWordFromPool(uword end, 44 static uword DecodeLoadWordFromPool(uword end,
45 Register* reg, 45 Register* reg,
46 intptr_t* index); 46 intptr_t* index);
47
48 // Encodes a load sequence ending at 'end'. Encodes a fixed length two
49 // instruction load from the pool pointer in PP using the destination
50 // register reg as a temporary for the base address.
51 static void EncodeLoadWordFromPoolFixed(uword end, int32_t offset);
52
53 static intptr_t OffsetFromPPIndex(intptr_t index);
47 }; 54 };
48 55
49 56
50 class CallPattern : public ValueObject { 57 class CallPattern : public ValueObject {
51 public: 58 public:
52 CallPattern(uword pc, const Code& code); 59 CallPattern(uword pc, const Code& code);
53 60
54 RawICData* IcData(); 61 RawICData* IcData();
55 RawArray* ClosureArgumentsDescriptor(); 62 RawArray* ClosureArgumentsDescriptor();
56 63
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94 101
95 private: 102 private:
96 const uword pc_; 103 const uword pc_;
97 104
98 DISALLOW_COPY_AND_ASSIGN(JumpPattern); 105 DISALLOW_COPY_AND_ASSIGN(JumpPattern);
99 }; 106 };
100 107
101 } // namespace dart 108 } // namespace dart
102 109
103 #endif // VM_INSTRUCTIONS_ARM64_H_ 110 #endif // VM_INSTRUCTIONS_ARM64_H_
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