Adds debugger patching to arm64.

runtime/vm/instructions_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm64.h"
 #include "vm/cpu.h"
@@ skipping 16 matching lines @@
 
   Register reg;
   ic_data_load_end_ =
       InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize,
                                                  &reg,
                                                  &target_address_pool_index_);
   ASSERT(reg == IP0);
 }
 
 
+intptr_t InstructionPattern::OffsetFromPPIndex(intptr_t index) {
+  return Array::element_offset(index);
+}
+
+
 // Decodes a load sequence ending at 'end' (the last instruction of the load
 // sequence is the instruction before the one at end).  Returns a pointer to
 // the first instruction in the sequence.  Returns the register being loaded
 // and the loaded object in the output parameters 'reg' and 'obj'
 // respectively.
 uword InstructionPattern::DecodeLoadObject(uword end,
                                            const Array& object_pool,
                                            Register* reg,
                                            Object* obj) {
   // 1. LoadWordFromPool
@@ skipping 93 matching lines @@
 // Decodes a load sequence ending at 'end' (the last instruction of the load
 // sequence is the instruction before the one at end).  Returns a pointer to
 // the first instruction in the sequence.  Returns the register being loaded
 // and the index in the pool being read from in the output parameters 'reg'
 // and 'index' respectively.
 uword InstructionPattern::DecodeLoadWordFromPool(uword end,
                                                  Register* reg,
                                                  intptr_t* index) {
   // 1. ldr dst, [pp, offset]
   // or
-  // 2. movz dst, low_offset, 0
+  // 2. add dst, pp, #offset_hi12
+  //    ldr dst [dst, #offset_lo12]
+  // or
+  // 3. movz dst, low_offset, 0
   //    movk dst, hi_offset, 1 (optional)
   //    ldr dst, [pp, dst]
   uword start = end - Instr::kInstrSize;
   Instr* instr = Instr::At(start);
   intptr_t offset = 0;
 
   // Last instruction is always an ldr into a 64-bit X register.
   ASSERT(instr->IsLoadStoreRegOp() && (instr->Bit(22) == 1) &&
         (instr->Bits(30, 2) == 3));
 
   // Grab the destination register from the ldr instruction.
   *reg = instr->RtField();
 
   if (instr->Bit(24) == 1) {
-    // pp + scaled unsigned 12-bit immediate offset.
+    // base + scaled unsigned 12-bit immediate offset.
     // Case 1.
-    offset = instr->Imm12Field() << 3;
+    offset |= (instr->Imm12Field() << 3);
+    if (instr->RnField() == *reg) {
+      start -= Instr::kInstrSize;
+      instr = Instr::At(start);
+      ASSERT(instr->IsAddSubImmOp());
+      ASSERT(instr->RnField() == PP);
+      ASSERT(instr->RdField() == *reg);
+      offset |= (instr->Imm12Field() << 12);
+    }
   } else {
     ASSERT(instr->Bits(10, 2) == 2);
     // We have to look at the preceding one or two instructions to find the
     // offset.
 
     start -= Instr::kInstrSize;
     instr = Instr::At(start);
     ASSERT(instr->IsMoveWideOp());
     ASSERT(instr->RdField() == *reg);
     if (instr->Bits(29, 2) == 2) {  // movz dst, low_offset, 0
@@ skipping 13 matching lines @@
       ASSERT(instr->HWField() == 0);
       offset |= instr->Imm16Field();
     }
   }
   ASSERT(Utils::IsAligned(offset, 8));
   *index = (offset - Array::data_offset()) / 8;
   return start;
 }
 
 
+// Encodes a load sequence ending at 'end'. Encodes a fixed length two
+// instruction load from the pool pointer in PP using the destination
+// register reg as a temporary for the base address.
+// Assumes that the location has already been validated for patching.
+void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
+                                                     int32_t offset) {
+  uword start = end - Instr::kInstrSize;
+  Instr* instr = Instr::At(start);
+  const int32_t upper12 = offset & 0x00fff000;
+  const int32_t lower12 = offset & 0x00000fff;
+  ASSERT((offset & 0xff000000) == 0);  // Can't encode > 24 bits.
+  ASSERT(((lower12 >> 3) << 3) == lower12);  // 8-byte aligned.
+  instr->SetImm12Bits(instr->InstructionBits(), lower12 >> 3);
+
+  start -= Instr::kInstrSize;
+  instr = Instr::At(start);
+  instr->SetImm12Bits(instr->InstructionBits(), upper12 >> 12);
+  instr->SetInstructionBits(instr->InstructionBits() | B22);
+}
+
+
 RawICData* CallPattern::IcData() {
   if (ic_data_.IsNull()) {
     Register reg;
     args_desc_load_end_ =
         InstructionPattern::DecodeLoadObject(ic_data_load_end_,
                                              object_pool_,
                                              &reg,
                                              &ic_data_);
     ASSERT(reg == R5);
   }
@@ skipping 113 matching lines @@
   movz0->SetInstructionBits((movz0_bits & ~kImm16Mask) | (h0 << kImm16Shift));
   movk1->SetInstructionBits((movk1_bits & ~kImm16Mask) | (h1 << kImm16Shift));
   movk2->SetInstructionBits((movk2_bits & ~kImm16Mask) | (h2 << kImm16Shift));
   movk3->SetInstructionBits((movk3_bits & ~kImm16Mask) | (h3 << kImm16Shift));
   CPU::FlushICache(pc_, 4 * Instr::kInstrSize);
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64