[assembler] Make register definitions constexpr

src/arm/assembler-arm.h

Index: src/arm/assembler-arm.h
diff --git a/src/arm/assembler-arm.h b/src/arm/assembler-arm.h
index 420d195f3d4e7c7e9ada4a86841453b44f38829e..9adf3095573acbd7195492d2f7a5669884469df9 100644
--- a/src/arm/assembler-arm.h
+++ b/src/arm/assembler-arm.h
@@ -114,7 +114,7 @@ struct Register {
     kCode_no_reg = -1
   };
 
-  static const int kNumRegisters = Code::kAfterLast;
+  static constexpr int kNumRegisters = Code::kAfterLast;
 
   static Register from_code(int code) {
     DCHECK(code >= 0);
@@ -144,13 +144,13 @@ struct Register {
 // r7: context register
 // r8: constant pool pointer register if FLAG_enable_embedded_constant_pool.
 // r9: lithium scratch
-#define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R};
+#define DECLARE_REGISTER(R) constexpr Register R = {Register::kCode_##R};
 GENERAL_REGISTERS(DECLARE_REGISTER)
 #undef DECLARE_REGISTER
-const Register no_reg = {Register::kCode_no_reg};
+constexpr Register no_reg = {Register::kCode_no_reg};
 
-static const bool kSimpleFPAliasing = false;
-static const bool kSimdMaskRegisters = false;
+constexpr bool kSimpleFPAliasing = false;
+constexpr bool kSimdMaskRegisters = false;
 
 // Single word VFP register.
 struct SwVfpRegister {
@@ -162,9 +162,9 @@ struct SwVfpRegister {
     kCode_no_reg = -1
   };
 
-  static const int kMaxNumRegisters = Code::kAfterLast;
+  static constexpr int kMaxNumRegisters = Code::kAfterLast;
 
-  static const int kSizeInBytes = 4;
+  static constexpr int kSizeInBytes = 4;
 
   bool is_valid() const { return 0 <= reg_code && reg_code < 32; }
   bool is(SwVfpRegister reg) const { return reg_code == reg.reg_code; }
@@ -201,7 +201,7 @@ struct DwVfpRegister {
     kCode_no_reg = -1
   };
 
-  static const int kMaxNumRegisters = Code::kAfterLast;
+  static constexpr int kMaxNumRegisters = Code::kAfterLast;
 
   inline static int NumRegisters();
 
@@ -209,7 +209,7 @@ struct DwVfpRegister {
   // hold 0.0, that does not fit in the immediate field of vmov instructions.
   //  d14: 0.0
   //  d15: scratch register.
-  static const int kSizeInBytes = 8;
+  static constexpr int kSizeInBytes = 8;
 
   bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
   bool is(DwVfpRegister reg) const { return reg_code == reg.reg_code; }
@@ -242,10 +242,9 @@ typedef DwVfpRegister DoubleRegister;
 // Double word VFP register d0-15.
 struct LowDwVfpRegister {
  public:
-  static const int kMaxNumLowRegisters = 16;
-  operator DwVfpRegister() const {
-    DwVfpRegister r = { reg_code };
-    return r;
+  static constexpr int kMaxNumLowRegisters = 16;
+  constexpr operator DwVfpRegister() const {
+    return DwVfpRegister { reg_code };
   }
   static LowDwVfpRegister from_code(int code) {
     LowDwVfpRegister r = { code };
@@ -282,7 +281,7 @@ struct LowDwVfpRegister {
 
 // Quad word NEON register.
 struct QwNeonRegister {
-  static const int kMaxNumRegisters = 16;
+  static constexpr int kMaxNumRegisters = 16;
 
   static QwNeonRegister from_code(int code) {
     QwNeonRegister r = { code };
@@ -328,102 +327,100 @@ typedef QwNeonRegister Simd128Register;
 
 // Support for the VFP registers s0 to s31 (d0 to d15).
 // Note that "s(N):s(N+1)" is the same as "d(N/2)".
-const SwVfpRegister s0  = {  0 };
-const SwVfpRegister s1  = {  1 };
-const SwVfpRegister s2  = {  2 };
-const SwVfpRegister s3  = {  3 };
-const SwVfpRegister s4  = {  4 };
-const SwVfpRegister s5  = {  5 };
-const SwVfpRegister s6  = {  6 };
-const SwVfpRegister s7  = {  7 };
-const SwVfpRegister s8  = {  8 };
-const SwVfpRegister s9  = {  9 };
-const SwVfpRegister s10 = { 10 };
-const SwVfpRegister s11 = { 11 };
-const SwVfpRegister s12 = { 12 };
-const SwVfpRegister s13 = { 13 };
-const SwVfpRegister s14 = { 14 };
-const SwVfpRegister s15 = { 15 };
-const SwVfpRegister s16 = { 16 };
-const SwVfpRegister s17 = { 17 };
-const SwVfpRegister s18 = { 18 };
-const SwVfpRegister s19 = { 19 };
-const SwVfpRegister s20 = { 20 };
-const SwVfpRegister s21 = { 21 };
-const SwVfpRegister s22 = { 22 };
-const SwVfpRegister s23 = { 23 };
-const SwVfpRegister s24 = { 24 };
-const SwVfpRegister s25 = { 25 };
-const SwVfpRegister s26 = { 26 };
-const SwVfpRegister s27 = { 27 };
-const SwVfpRegister s28 = { 28 };
-const SwVfpRegister s29 = { 29 };
-const SwVfpRegister s30 = { 30 };
-const SwVfpRegister s31 = { 31 };
-
-const DwVfpRegister no_dreg = { -1 };
-const LowDwVfpRegister d0 = { 0 };
-const LowDwVfpRegister d1 = { 1 };
-const LowDwVfpRegister d2 = { 2 };
-const LowDwVfpRegister d3 = { 3 };
-const LowDwVfpRegister d4 = { 4 };
-const LowDwVfpRegister d5 = { 5 };
-const LowDwVfpRegister d6 = { 6 };
-const LowDwVfpRegister d7 = { 7 };
-const LowDwVfpRegister d8 = { 8 };
-const LowDwVfpRegister d9 = { 9 };
-const LowDwVfpRegister d10 = { 10 };
-const LowDwVfpRegister d11 = { 11 };
-const LowDwVfpRegister d12 = { 12 };
-const LowDwVfpRegister d13 = { 13 };
-const LowDwVfpRegister d14 = { 14 };
-const LowDwVfpRegister d15 = { 15 };
-const DwVfpRegister d16 = { 16 };
-const DwVfpRegister d17 = { 17 };
-const DwVfpRegister d18 = { 18 };
-const DwVfpRegister d19 = { 19 };
-const DwVfpRegister d20 = { 20 };
-const DwVfpRegister d21 = { 21 };
-const DwVfpRegister d22 = { 22 };
-const DwVfpRegister d23 = { 23 };
-const DwVfpRegister d24 = { 24 };
-const DwVfpRegister d25 = { 25 };
-const DwVfpRegister d26 = { 26 };
-const DwVfpRegister d27 = { 27 };
-const DwVfpRegister d28 = { 28 };
-const DwVfpRegister d29 = { 29 };
-const DwVfpRegister d30 = { 30 };
-const DwVfpRegister d31 = { 31 };
-
-const QwNeonRegister q0  = {  0 };
-const QwNeonRegister q1  = {  1 };
-const QwNeonRegister q2  = {  2 };
-const QwNeonRegister q3  = {  3 };
-const QwNeonRegister q4  = {  4 };
-const QwNeonRegister q5  = {  5 };
-const QwNeonRegister q6  = {  6 };
-const QwNeonRegister q7  = {  7 };
-const QwNeonRegister q8  = {  8 };
-const QwNeonRegister q9  = {  9 };
-const QwNeonRegister q10 = { 10 };
-const QwNeonRegister q11 = { 11 };
-const QwNeonRegister q12 = { 12 };
-const QwNeonRegister q13 = { 13 };
-const QwNeonRegister q14 = { 14 };
-const QwNeonRegister q15 = { 15 };
-
-
-// Aliases for double registers.  Defined using #define instead of
-// "static const DwVfpRegister&" because Clang complains otherwise when a
-// compilation unit that includes this header doesn't use the variables.
-#define kFirstCalleeSavedDoubleReg d8
-#define kLastCalleeSavedDoubleReg d15
+constexpr SwVfpRegister s0  = {  0 };
+constexpr SwVfpRegister s1  = {  1 };
+constexpr SwVfpRegister s2  = {  2 };
+constexpr SwVfpRegister s3  = {  3 };
+constexpr SwVfpRegister s4  = {  4 };
+constexpr SwVfpRegister s5  = {  5 };
+constexpr SwVfpRegister s6  = {  6 };
+constexpr SwVfpRegister s7  = {  7 };
+constexpr SwVfpRegister s8  = {  8 };
+constexpr SwVfpRegister s9  = {  9 };
+constexpr SwVfpRegister s10 = { 10 };
+constexpr SwVfpRegister s11 = { 11 };
+constexpr SwVfpRegister s12 = { 12 };
+constexpr SwVfpRegister s13 = { 13 };
+constexpr SwVfpRegister s14 = { 14 };
+constexpr SwVfpRegister s15 = { 15 };
+constexpr SwVfpRegister s16 = { 16 };
+constexpr SwVfpRegister s17 = { 17 };
+constexpr SwVfpRegister s18 = { 18 };
+constexpr SwVfpRegister s19 = { 19 };
+constexpr SwVfpRegister s20 = { 20 };
+constexpr SwVfpRegister s21 = { 21 };
+constexpr SwVfpRegister s22 = { 22 };
+constexpr SwVfpRegister s23 = { 23 };
+constexpr SwVfpRegister s24 = { 24 };
+constexpr SwVfpRegister s25 = { 25 };
+constexpr SwVfpRegister s26 = { 26 };
+constexpr SwVfpRegister s27 = { 27 };
+constexpr SwVfpRegister s28 = { 28 };
+constexpr SwVfpRegister s29 = { 29 };
+constexpr SwVfpRegister s30 = { 30 };
+constexpr SwVfpRegister s31 = { 31 };
+
+constexpr DwVfpRegister no_dreg = { -1 };
+constexpr LowDwVfpRegister d0 = { 0 };
+constexpr LowDwVfpRegister d1 = { 1 };
+constexpr LowDwVfpRegister d2 = { 2 };
+constexpr LowDwVfpRegister d3 = { 3 };
+constexpr LowDwVfpRegister d4 = { 4 };
+constexpr LowDwVfpRegister d5 = { 5 };
+constexpr LowDwVfpRegister d6 = { 6 };
+constexpr LowDwVfpRegister d7 = { 7 };
+constexpr LowDwVfpRegister d8 = { 8 };
+constexpr LowDwVfpRegister d9 = { 9 };
+constexpr LowDwVfpRegister d10 = { 10 };
+constexpr LowDwVfpRegister d11 = { 11 };
+constexpr LowDwVfpRegister d12 = { 12 };
+constexpr LowDwVfpRegister d13 = { 13 };
+constexpr LowDwVfpRegister d14 = { 14 };
+constexpr LowDwVfpRegister d15 = { 15 };
+constexpr DwVfpRegister d16 = { 16 };
+constexpr DwVfpRegister d17 = { 17 };
+constexpr DwVfpRegister d18 = { 18 };
+constexpr DwVfpRegister d19 = { 19 };
+constexpr DwVfpRegister d20 = { 20 };
+constexpr DwVfpRegister d21 = { 21 };
+constexpr DwVfpRegister d22 = { 22 };
+constexpr DwVfpRegister d23 = { 23 };
+constexpr DwVfpRegister d24 = { 24 };
+constexpr DwVfpRegister d25 = { 25 };
+constexpr DwVfpRegister d26 = { 26 };
+constexpr DwVfpRegister d27 = { 27 };
+constexpr DwVfpRegister d28 = { 28 };
+constexpr DwVfpRegister d29 = { 29 };
+constexpr DwVfpRegister d30 = { 30 };
+constexpr DwVfpRegister d31 = { 31 };
+
+constexpr QwNeonRegister q0  = {  0 };
+constexpr QwNeonRegister q1  = {  1 };
+constexpr QwNeonRegister q2  = {  2 };
+constexpr QwNeonRegister q3  = {  3 };
+constexpr QwNeonRegister q4  = {  4 };
+constexpr QwNeonRegister q5  = {  5 };
+constexpr QwNeonRegister q6  = {  6 };
+constexpr QwNeonRegister q7  = {  7 };
+constexpr QwNeonRegister q8  = {  8 };
+constexpr QwNeonRegister q9  = {  9 };
+constexpr QwNeonRegister q10 = { 10 };
+constexpr QwNeonRegister q11 = { 11 };
+constexpr QwNeonRegister q12 = { 12 };
+constexpr QwNeonRegister q13 = { 13 };
+constexpr QwNeonRegister q14 = { 14 };
+constexpr QwNeonRegister q15 = { 15 };
+
+
+// Aliases for double registers.
+constexpr LowDwVfpRegister kFirstCalleeSavedDoubleReg = d8;
+constexpr LowDwVfpRegister kLastCalleeSavedDoubleReg = d15;
 // kDoubleRegZero and kScratchDoubleReg must pair to form kScratchQuadReg. SIMD
 // code depends on kDoubleRegZero before kScratchDoubleReg.
-#define kDoubleRegZero d14
-#define kScratchDoubleReg d15
+constexpr LowDwVfpRegister kDoubleRegZero  = d14;
+constexpr LowDwVfpRegister kScratchDoubleReg = d15;
 // After using kScratchQuadReg, kDoubleRegZero must be reset to 0.
-#define kScratchQuadReg q7
+constexpr QwNeonRegister kScratchQuadReg = q7;
 
 // Coprocessor register
 struct CRegister {
@@ -443,24 +440,24 @@ struct CRegister {
 };
 
 
-const CRegister no_creg = { -1 };
+constexpr CRegister no_creg = { -1 };
 
-const CRegister cr0  = {  0 };
-const CRegister cr1  = {  1 };
-const CRegister cr2  = {  2 };
-const CRegister cr3  = {  3 };
-const CRegister cr4  = {  4 };
-const CRegister cr5  = {  5 };
-const CRegister cr6  = {  6 };
-const CRegister cr7  = {  7 };
-const CRegister cr8  = {  8 };
-const CRegister cr9  = {  9 };
-const CRegister cr10 = { 10 };
-const CRegister cr11 = { 11 };
-const CRegister cr12 = { 12 };
-const CRegister cr13 = { 13 };
-const CRegister cr14 = { 14 };
-const CRegister cr15 = { 15 };
+constexpr CRegister cr0  = {  0 };
+constexpr CRegister cr1  = {  1 };
+constexpr CRegister cr2  = {  2 };
+constexpr CRegister cr3  = {  3 };
+constexpr CRegister cr4  = {  4 };
+constexpr CRegister cr5  = {  5 };
+constexpr CRegister cr6  = {  6 };
+constexpr CRegister cr7  = {  7 };
+constexpr CRegister cr8  = {  8 };
+constexpr CRegister cr9  = {  9 };
+constexpr CRegister cr10 = { 10 };
+constexpr CRegister cr11 = { 11 };
+constexpr CRegister cr12 = { 12 };
+constexpr CRegister cr13 = { 13 };
+constexpr CRegister cr14 = { 14 };
+constexpr CRegister cr15 = { 15 };
 
 
 // Coprocessor number
@@ -671,8 +668,8 @@ class NeonListOperand BASE_EMBEDDED {
 struct VmovIndex {
   unsigned char index;
 };
-const VmovIndex VmovIndexLo = { 0 };
-const VmovIndex VmovIndexHi = { 1 };
+constexpr VmovIndex VmovIndexLo = { 0 };
+constexpr VmovIndex VmovIndexHi = { 1 };
 
 class Assembler : public AssemblerBase {
  public:
@@ -760,24 +757,24 @@ class Assembler : public AssemblerBase {
   // Here we are patching the address in the constant pool, not the actual call
   // instruction.  The address in the constant pool is the same size as a
   // pointer.
-  static const int kSpecialTargetSize = kPointerSize;
+  static constexpr int kSpecialTargetSize = kPointerSize;
 
   // Size of an instruction.
-  static const int kInstrSize = sizeof(Instr);
+  static constexpr int kInstrSize = sizeof(Instr);
 
   // Distance between start of patched debug break slot and the emitted address
   // to jump to.
   // Patched debug break slot code is:
   //  ldr  ip, [pc, #0]   @ emited address and start
   //  blx  ip
-  static const int kPatchDebugBreakSlotAddressOffset = 2 * kInstrSize;
+  static constexpr int kPatchDebugBreakSlotAddressOffset = 2 * kInstrSize;
 
   // Difference between address of current opcode and value read from pc
   // register.
-  static const int kPcLoadDelta = 8;
+  static constexpr int kPcLoadDelta = 8;
 
-  static const int kDebugBreakSlotInstructions = 4;
-  static const int kDebugBreakSlotLength =
+  static constexpr int kDebugBreakSlotInstructions = 4;
+  static constexpr int kDebugBreakSlotLength =
       kDebugBreakSlotInstructions * kInstrSize;
 
   // ---------------------------------------------------------------------------
@@ -1592,12 +1589,14 @@ class Assembler : public AssemblerBase {
   // reach +/-4KB for integer PC-relative loads and +/-1KB for floating-point
   // PC-relative loads, thereby defining a maximum distance between the
   // instruction and the accessed constant.
-  static const int kMaxDistToIntPool = 4*KB;
-  static const int kMaxDistToFPPool = 1*KB;
+  static constexpr int kMaxDistToIntPool = 4 * KB;
+  static constexpr int kMaxDistToFPPool = 1 * KB;
   // All relocations could be integer, it therefore acts as the limit.
-  static const int kMinNumPendingConstants = 4;
-  static const int kMaxNumPending32Constants = kMaxDistToIntPool / kInstrSize;
-  static const int kMaxNumPending64Constants = kMaxDistToFPPool / kInstrSize;
+  static constexpr int kMinNumPendingConstants = 4;
+  static constexpr int kMaxNumPending32Constants =
+      kMaxDistToIntPool / kInstrSize;
+  static constexpr int kMaxNumPending64Constants =
+      kMaxDistToFPPool / kInstrSize;
 
   // Postpone the generation of the constant pool for the specified number of
   // instructions.
@@ -1700,7 +1699,7 @@ class Assembler : public AssemblerBase {
   // the generated instructions. This is so that multi-instruction sequences do
   // not have to check for overflow. The same is true for writes of large
   // relocation info entries.
-  static const int kGap = 32;
+  static constexpr int kGap = 32;
 
   // Constant pool generation
   // Pools are emitted in the instruction stream, preferably after unconditional
@@ -1716,8 +1715,8 @@ class Assembler : public AssemblerBase {
   // expensive. By default we only check again once a number of instructions
   // has been generated. That also means that the sizing of the buffers is not
   // an exact science, and that we rely on some slop to not overrun buffers.
-  static const int kCheckPoolIntervalInst = 32;
-  static const int kCheckPoolInterval = kCheckPoolIntervalInst * kInstrSize;
+  static constexpr int kCheckPoolIntervalInst = 32;
+  static constexpr int kCheckPoolInterval = kCheckPoolIntervalInst * kInstrSize;
 
 
   // Emission of the constant pool may be blocked in some code sequences.
@@ -1731,7 +1730,7 @@ class Assembler : public AssemblerBase {
 
   // Relocation info generation
   // Each relocation is encoded as a variable size value
-  static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
+  static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize;
   RelocInfoWriter reloc_info_writer;
 
   // ConstantPoolEntry records are used during code generation as temporary
@@ -1785,7 +1784,7 @@ class Assembler : public AssemblerBase {
   friend class EnsureSpace;
 };
 
-static const int kNoCodeAgeSequenceLength = 3 * Assembler::kInstrSize;
+constexpr int kNoCodeAgeSequenceLength = 3 * Assembler::kInstrSize;
 
 class EnsureSpace BASE_EMBEDDED {
  public: