[assembler] Make register definitions constexpr

src/mips/assembler-mips.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 79 matching lines @@
 // to a few constants). If this is a problem, we could change the code
 // such that we use an enum in optimized mode, and the struct in debug
 // mode. This way we get the compile-time error checking in debug mode
 // and best performance in optimized code.
 
 
 // -----------------------------------------------------------------------------
 // Implementation of Register and FPURegister.
 
 struct Register {
-  static const int kCpRegister = 23;  // cp (s7) is the 23rd register.
+  static constexpr int kCpRegister = 23;  // cp (s7) is the 23rd register.
 
   enum Code {
 #define REGISTER_CODE(R) kCode_##R,
     GENERAL_REGISTERS(REGISTER_CODE)
 #undef REGISTER_CODE
         kAfterLast,
     kCode_no_reg = -1
   };
 
-  static const int kNumRegisters = Code::kAfterLast;
+  static constexpr int kNumRegisters = Code::kAfterLast;
 
 #if defined(V8_TARGET_LITTLE_ENDIAN)
-  static const int kMantissaOffset = 0;
-  static const int kExponentOffset = 4;
+  static constexpr int kMantissaOffset = 0;
+  static constexpr int kExponentOffset = 4;
 #elif defined(V8_TARGET_BIG_ENDIAN)
-  static const int kMantissaOffset = 4;
-  static const int kExponentOffset = 0;
+  static constexpr int kMantissaOffset = 4;
+  static constexpr int kExponentOffset = 0;
 #else
 #error Unknown endianness
 #endif
 
 
   static Register from_code(int code) {
-    DCHECK(code >= 0);
-    DCHECK(code < kNumRegisters);
-    Register r = {code};
-    return r;
+    DCHECK_LE(0, code);
+    DCHECK_GT(kNumRegisters, code);
+    return Register{code};
   }
   bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
   bool is(Register reg) const { return reg_code == reg.reg_code; }
   int code() const {
     DCHECK(is_valid());
     return reg_code;
   }
   int bit() const {
     DCHECK(is_valid());
     return 1 << reg_code;
   }
 
   // Unfortunately we can't make this private in a struct.
   int reg_code;
 };
 
 // s7: context register
 // s3: lithium scratch
 // s4: lithium scratch2
-#define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R};
+#define DECLARE_REGISTER(R) constexpr Register R = {Register::kCode_##R};
 GENERAL_REGISTERS(DECLARE_REGISTER)
 #undef DECLARE_REGISTER
-const Register no_reg = {Register::kCode_no_reg};
-
+constexpr Register no_reg = {Register::kCode_no_reg};
 
 int ToNumber(Register reg);
 
 Register ToRegister(int num);
 
-static const bool kSimpleFPAliasing = true;
-static const bool kSimdMaskRegisters = false;
+constexpr bool kSimpleFPAliasing = true;
+constexpr bool kSimdMaskRegisters = false;
 
 // Coprocessor register.
 struct FPURegister {
   enum Code {
 #define REGISTER_CODE(R) kCode_##R,
     DOUBLE_REGISTERS(REGISTER_CODE)
 #undef REGISTER_CODE
         kAfterLast,
     kCode_no_reg = -1
   };
 
-  static const int kMaxNumRegisters = Code::kAfterLast;
+  static constexpr int kMaxNumRegisters = Code::kAfterLast;
 
   inline static int NumRegisters();
 
   // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
   // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
   // number of Double regs (64-bit regs, or FPU-reg-pairs).
 
   bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
   bool is(FPURegister reg) const { return reg_code == reg.reg_code; }
   FPURegister low() const {
@@ skipping 48 matching lines @@
 // but it is not in common use. Someday we will want to support this in v8.)
 
 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
 typedef FPURegister FloatRegister;
 
 typedef FPURegister DoubleRegister;
 
 // TODO(mips) Define SIMD registers.
 typedef FPURegister Simd128Register;
 
-const DoubleRegister no_freg = {-1};
+constexpr DoubleRegister no_freg = {-1};
 
-const DoubleRegister f0 = {0};  // Return value in hard float mode.
-const DoubleRegister f1 = {1};
-const DoubleRegister f2 = {2};
-const DoubleRegister f3 = {3};
-const DoubleRegister f4 = {4};
-const DoubleRegister f5 = {5};
-const DoubleRegister f6 = {6};
-const DoubleRegister f7 = {7};
-const DoubleRegister f8 = {8};
-const DoubleRegister f9 = {9};
-const DoubleRegister f10 = {10};
-const DoubleRegister f11 = {11};
-const DoubleRegister f12 = {12};  // Arg 0 in hard float mode.
-const DoubleRegister f13 = {13};
-const DoubleRegister f14 = {14};  // Arg 1 in hard float mode.
-const DoubleRegister f15 = {15};
-const DoubleRegister f16 = {16};
-const DoubleRegister f17 = {17};
-const DoubleRegister f18 = {18};
-const DoubleRegister f19 = {19};
-const DoubleRegister f20 = {20};
-const DoubleRegister f21 = {21};
-const DoubleRegister f22 = {22};
-const DoubleRegister f23 = {23};
-const DoubleRegister f24 = {24};
-const DoubleRegister f25 = {25};
-const DoubleRegister f26 = {26};
-const DoubleRegister f27 = {27};
-const DoubleRegister f28 = {28};
-const DoubleRegister f29 = {29};
-const DoubleRegister f30 = {30};
-const DoubleRegister f31 = {31};
+constexpr DoubleRegister f0 = {0};  // Return value in hard float mode.
+constexpr DoubleRegister f1 = {1};
+constexpr DoubleRegister f2 = {2};
+constexpr DoubleRegister f3 = {3};
+constexpr DoubleRegister f4 = {4};
+constexpr DoubleRegister f5 = {5};
+constexpr DoubleRegister f6 = {6};
+constexpr DoubleRegister f7 = {7};
+constexpr DoubleRegister f8 = {8};
+constexpr DoubleRegister f9 = {9};
+constexpr DoubleRegister f10 = {10};
+constexpr DoubleRegister f11 = {11};
+constexpr DoubleRegister f12 = {12};  // Arg 0 in hard float mode.
+constexpr DoubleRegister f13 = {13};
+constexpr DoubleRegister f14 = {14};  // Arg 1 in hard float mode.
+constexpr DoubleRegister f15 = {15};
+constexpr DoubleRegister f16 = {16};
+constexpr DoubleRegister f17 = {17};
+constexpr DoubleRegister f18 = {18};
+constexpr DoubleRegister f19 = {19};
+constexpr DoubleRegister f20 = {20};
+constexpr DoubleRegister f21 = {21};
+constexpr DoubleRegister f22 = {22};
+constexpr DoubleRegister f23 = {23};
+constexpr DoubleRegister f24 = {24};
+constexpr DoubleRegister f25 = {25};
+constexpr DoubleRegister f26 = {26};
+constexpr DoubleRegister f27 = {27};
+constexpr DoubleRegister f28 = {28};
+constexpr DoubleRegister f29 = {29};
+constexpr DoubleRegister f30 = {30};
+constexpr DoubleRegister f31 = {31};
 
 // Register aliases.
 // cp is assumed to be a callee saved register.
-// Defined using #define instead of "static const Register&" because Clang
-// complains otherwise when a compilation unit that includes this header
-// doesn't use the variables.
-#define kRootRegister s6
-#define cp s7
-#define kLithiumScratchReg s3
-#define kLithiumScratchReg2 s4
-#define kLithiumScratchDouble f30
-#define kDoubleRegZero f28
+constexpr Register kRootRegister = s6;
+constexpr Register cp = s7;
+constexpr Register kLithiumScratchReg = s3;
+constexpr Register kLithiumScratchReg2 = s4;
+constexpr DoubleRegister kLithiumScratchDouble = f30;
+constexpr DoubleRegister kDoubleRegZero = f28;
 // Used on mips32r6 for compare operations.
-#define kDoubleCompareReg f26
+constexpr DoubleRegister kDoubleCompareReg = f26;
 
 // FPU (coprocessor 1) control registers.
 // Currently only FCSR (#31) is implemented.
 struct FPUControlRegister {
   bool is_valid() const { return reg_code == kFCSRRegister; }
   bool is(FPUControlRegister creg) const { return reg_code == creg.reg_code; }
   int code() const {
     DCHECK(is_valid());
     return reg_code;
   }
   int bit() const {
     DCHECK(is_valid());
     return 1 << reg_code;
   }
   void setcode(int f) {
     reg_code = f;
     DCHECK(is_valid());
   }
   // Unfortunately we can't make this private in a struct.
   int reg_code;
 };
 
-const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
-const FPUControlRegister FCSR = { kFCSRRegister };
+constexpr FPUControlRegister no_fpucreg = {kInvalidFPUControlRegister};
+constexpr FPUControlRegister FCSR = {kFCSRRegister};
 
 // -----------------------------------------------------------------------------
 // Machine instruction Operands.
 
 // Class Operand represents a shifter operand in data processing instructions.
 class Operand BASE_EMBEDDED {
  public:
   // Immediate.
   INLINE(explicit Operand(int32_t immediate,
          RelocInfo::Mode rmode = RelocInfo::NONE32));
@@ skipping 174 matching lines @@
         instruction_payload - kInstructionsFor32BitConstant * kInstrSize, code,
         target);
   }
 
   // This sets the internal reference at the pc.
   inline static void deserialization_set_target_internal_reference_at(
       Isolate* isolate, Address pc, Address target,
       RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
 
   // Size of an instruction.
-  static const int kInstrSize = sizeof(Instr);
+  static constexpr int kInstrSize = sizeof(Instr);
 
   // Difference between address of current opcode and target address offset.
-  static const int kBranchPCOffset = 4;
+  static constexpr int kBranchPCOffset = 4;
 
   // Here we are patching the address in the LUI/ORI instruction pair.
   // These values are used in the serialization process and must be zero for
   // MIPS platform, as Code, Embedded Object or External-reference pointers
   // are split across two consecutive instructions and don't exist separately
   // in the code, so the serializer should not step forwards in memory after
   // a target is resolved and written.
-  static const int kSpecialTargetSize = 0;
+  static constexpr int kSpecialTargetSize = 0;
 
   // Number of consecutive instructions used to store 32bit constant. This
   // constant is used in RelocInfo::target_address_address() function to tell
   // serializer address of the instruction that follows LUI/ORI instruction
   // pair.
-  static const int kInstructionsFor32BitConstant = 2;
+  static constexpr int kInstructionsFor32BitConstant = 2;
 
   // Distance between the instruction referring to the address of the call
   // target and the return address.
 #ifdef _MIPS_ARCH_MIPS32R6
-  static const int kCallTargetAddressOffset = 3 * kInstrSize;
+  static constexpr int kCallTargetAddressOffset = 3 * kInstrSize;
 #else
-  static const int kCallTargetAddressOffset = 4 * kInstrSize;
+  static constexpr int kCallTargetAddressOffset = 4 * kInstrSize;
 #endif
 
   // Distance between start of patched debug break slot and the emitted address
   // to jump to.
-  static const int kPatchDebugBreakSlotAddressOffset = 4 * kInstrSize;
+  static constexpr int kPatchDebugBreakSlotAddressOffset = 4 * kInstrSize;
 
   // Difference between address of current opcode and value read from pc
   // register.
-  static const int kPcLoadDelta = 4;
+  static constexpr int kPcLoadDelta = 4;
 
 #ifdef _MIPS_ARCH_MIPS32R6
-  static const int kDebugBreakSlotInstructions = 3;
+  static constexpr int kDebugBreakSlotInstructions = 3;
 #else
-  static const int kDebugBreakSlotInstructions = 4;
+  static constexpr int kDebugBreakSlotInstructions = 4;
 #endif
-  static const int kDebugBreakSlotLength =
+  static constexpr int kDebugBreakSlotLength =
       kDebugBreakSlotInstructions * kInstrSize;
 
   // Max offset for instructions with 16-bit offset field
-  static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
+  static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1;
 
   // Max offset for compact branch instructions with 26-bit offset field
-  static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
+  static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
 
 #ifdef _MIPS_ARCH_MIPS32R6
-  static const int kTrampolineSlotsSize = 2 * kInstrSize;
+  static constexpr int kTrampolineSlotsSize = 2 * kInstrSize;
 #else
-  static const int kTrampolineSlotsSize = 4 * kInstrSize;
+  static constexpr int kTrampolineSlotsSize = 4 * kInstrSize;
 #endif
 
   // ---------------------------------------------------------------------------
   // Code generation.
 
   // Insert the smallest number of nop instructions
   // possible to align the pc offset to a multiple
   // of m. m must be a power of 2 (>= 4).
   void Align(int m);
   // Insert the smallest number of zero bytes possible to align the pc offset
@@ skipping 688 matching lines @@
   inline void CheckTrampolinePoolQuick(int extra_instructions = 0);
 
   inline void CheckBuffer();
 
  private:
   inline static void set_target_internal_reference_encoded_at(Address pc,
                                                               Address target);
 
   // Buffer size and constant pool distance are checked together at regular
   // intervals of kBufferCheckInterval emitted bytes.
-  static const int kBufferCheckInterval = 1*KB/2;
+  static constexpr int kBufferCheckInterval = 1 * KB / 2;
 
   // Code generation.
   // The relocation writer's position is at least kGap bytes below the end of
   // the generated instructions. This is so that multi-instruction sequences do
   // not have to check for overflow. The same is true for writes of large
   // relocation info entries.
-  static const int kGap = 32;
-
+  static constexpr int kGap = 32;
 
   // Repeated checking whether the trampoline pool should be emitted is rather
   // expensive. By default we only check again once a number of instructions
   // has been generated.
-  static const int kCheckConstIntervalInst = 32;
-  static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
+  static constexpr int kCheckConstIntervalInst = 32;
+  static constexpr int kCheckConstInterval =
+      kCheckConstIntervalInst * kInstrSize;
 
   int next_buffer_check_;  // pc offset of next buffer check.
 
   // Emission of the trampoline pool may be blocked in some code sequences.
   int trampoline_pool_blocked_nesting_;  // Block emission if this is not zero.
   int no_trampoline_pool_before_;  // Block emission before this pc offset.
 
   // Keep track of the last emitted pool to guarantee a maximal distance.
   int last_trampoline_pool_end_;  // pc offset of the end of the last pool.
 
   // Automatic growth of the assembly buffer may be blocked for some sequences.
   bool block_buffer_growth_;  // Block growth when true.
 
   // Relocation information generation.
   // Each relocation is encoded as a variable size value.
-  static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
+  static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize;
   RelocInfoWriter reloc_info_writer;
 
   // The bound position, before this we cannot do instruction elimination.
   int last_bound_pos_;
 
   // Readable constants for compact branch handling in emit()
   enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true };
 
   // Code emission.
   void GrowBuffer();
@@ skipping 133 matching lines @@
   };
 
   int32_t get_trampoline_entry(int32_t pos);
   int unbound_labels_count_;
   // If trampoline is emitted, generated code is becoming large. As this is
   // already a slow case which can possibly break our code generation for the
   // extreme case, we use this information to trigger different mode of
   // branch instruction generation, where we use jump instructions rather
   // than regular branch instructions.
   bool trampoline_emitted_;
-  static const int kInvalidSlotPos = -1;
+  static constexpr int kInvalidSlotPos = -1;
 
   // Internal reference positions, required for unbounded internal reference
   // labels.
   std::set<int> internal_reference_positions_;
   bool is_internal_reference(Label* L) {
     return internal_reference_positions_.find(L->pos()) !=
            internal_reference_positions_.end();
   }
 
   void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; }
@@ skipping 15 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_