Disentangle assembler from isolate.

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 341 matching lines @@
   DCHECK(IsWasmGlobalReference(rmode_));
   return Assembler::target_address_at(pc_, host_);
 }
 
 uint32_t RelocInfo::wasm_function_table_size_reference() {
   DCHECK(IsWasmFunctionTableSizeReference(rmode_));
   return reinterpret_cast<uint32_t>(Assembler::target_address_at(pc_, host_));
 }
 
 void RelocInfo::unchecked_update_wasm_memory_reference(
-    Address address, ICacheFlushMode flush_mode) {
-  Assembler::set_target_address_at(isolate_, pc_, host_, address, flush_mode);
+    Isolate* isolate, Address address, ICacheFlushMode flush_mode) {
+  Assembler::set_target_address_at(isolate, pc_, host_, address, flush_mode);
 }
 
-void RelocInfo::unchecked_update_wasm_size(uint32_t size,
+void RelocInfo::unchecked_update_wasm_size(Isolate* isolate, uint32_t size,
                                            ICacheFlushMode flush_mode) {
-  Assembler::set_target_address_at(isolate_, pc_, host_,
+  Assembler::set_target_address_at(isolate, pc_, host_,
                                    reinterpret_cast<Address>(size), flush_mode);
 }
 
 // -----------------------------------------------------------------------------
 // Implementation of Operand and MemOperand
 // See assembler-arm-inl.h for inlined constructors
 
 Operand::Operand(Handle<Object> handle) {
   AllowDeferredHandleDereference using_raw_address;
   rm_ = no_reg;
@@ skipping 165 matching lines @@
 const Instr kLdrRegFpOffsetPattern =
     al | B26 | L | Offset | Register::kCode_fp * B16;
 const Instr kStrRegFpOffsetPattern =
     al | B26 | Offset | Register::kCode_fp * B16;
 const Instr kLdrRegFpNegOffsetPattern =
     al | B26 | L | NegOffset | Register::kCode_fp * B16;
 const Instr kStrRegFpNegOffsetPattern =
     al | B26 | NegOffset | Register::kCode_fp * B16;
 const Instr kLdrStrInstrTypeMask = 0xffff0000;
 
-Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
-    : AssemblerBase(isolate, buffer, buffer_size),
+Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
+    : AssemblerBase(isolate_data, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
       pending_32_bit_constants_(),
       pending_64_bit_constants_(),
       constant_pool_builder_(kLdrMaxReachBits, kVldrMaxReachBits) {
   pending_32_bit_constants_.reserve(kMinNumPendingConstants);
   pending_64_bit_constants_.reserve(kMinNumPendingConstants);
   reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
   next_buffer_check_ = 0;
   const_pool_blocked_nesting_ = 0;
   no_const_pool_before_ = 0;
@@ skipping 368 matching lines @@
     //   For ARMv6: target24 => target8_2:target8_1:target8_0
     //      mov dst, #target8_0
     //      orr dst, dst, #target8_1 << 8
     //      orr dst, dst, #target8_2 << 16
 
     uint32_t target24 = target_pos + (Code::kHeaderSize - kHeapObjectTag);
     DCHECK(is_uint24(target24));
     if (is_uint8(target24)) {
       // If the target fits in a byte then only patch with a mov
       // instruction.
-      CodePatcher patcher(isolate(), reinterpret_cast<byte*>(buffer_ + pos), 1,
-                          CodePatcher::DONT_FLUSH);
-      patcher.masm()->mov(dst, Operand(target24));
+      PatchingAssembler patcher(isolate_data(),
+                                reinterpret_cast<byte*>(buffer_ + pos), 1);
+      patcher.mov(dst, Operand(target24));
     } else {
       uint16_t target16_0 = target24 & kImm16Mask;
       uint16_t target16_1 = target24 >> 16;
       if (CpuFeatures::IsSupported(ARMv7)) {
         // Patch with movw/movt.
         if (target16_1 == 0) {
-          CodePatcher patcher(isolate(), reinterpret_cast<byte*>(buffer_ + pos),
-                              1, CodePatcher::DONT_FLUSH);
-          CpuFeatureScope scope(patcher.masm(), ARMv7);
-          patcher.masm()->movw(dst, target16_0);
+          PatchingAssembler patcher(isolate_data(),
+                                    reinterpret_cast<byte*>(buffer_ + pos), 1);
+          CpuFeatureScope scope(&patcher, ARMv7);
+          patcher.movw(dst, target16_0);
         } else {
-          CodePatcher patcher(isolate(), reinterpret_cast<byte*>(buffer_ + pos),
-                              2, CodePatcher::DONT_FLUSH);
-          CpuFeatureScope scope(patcher.masm(), ARMv7);
-          patcher.masm()->movw(dst, target16_0);
-          patcher.masm()->movt(dst, target16_1);
+          PatchingAssembler patcher(isolate_data(),
+                                    reinterpret_cast<byte*>(buffer_ + pos), 2);
+          CpuFeatureScope scope(&patcher, ARMv7);
+          patcher.movw(dst, target16_0);
+          patcher.movt(dst, target16_1);
         }
       } else {
         // Patch with a sequence of mov/orr/orr instructions.
         uint8_t target8_0 = target16_0 & kImm8Mask;
         uint8_t target8_1 = target16_0 >> 8;
         uint8_t target8_2 = target16_1 & kImm8Mask;
         if (target8_2 == 0) {
-          CodePatcher patcher(isolate(), reinterpret_cast<byte*>(buffer_ + pos),
-                              2, CodePatcher::DONT_FLUSH);
-          patcher.masm()->mov(dst, Operand(target8_0));
-          patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
+          PatchingAssembler patcher(isolate_data(),
+                                    reinterpret_cast<byte*>(buffer_ + pos), 2);
+          patcher.mov(dst, Operand(target8_0));
+          patcher.orr(dst, dst, Operand(target8_1 << 8));
         } else {
-          CodePatcher patcher(isolate(), reinterpret_cast<byte*>(buffer_ + pos),
-                              3, CodePatcher::DONT_FLUSH);
-          patcher.masm()->mov(dst, Operand(target8_0));
-          patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
-          patcher.masm()->orr(dst, dst, Operand(target8_2 << 16));
+          PatchingAssembler patcher(isolate_data(),
+                                    reinterpret_cast<byte*>(buffer_ + pos), 3);
+          patcher.mov(dst, Operand(target8_0));
+          patcher.orr(dst, dst, Operand(target8_1 << 8));
+          patcher.orr(dst, dst, Operand(target8_2 << 16));
         }
       }
     }
     return;
   }
   int imm26 = target_pos - (pos + kPcLoadDelta);
   DCHECK_EQ(5 * B25, instr & 7 * B25);  // b, bl, or blx imm24
   if (Instruction::ConditionField(instr) == kSpecialCondition) {
     // blx uses bit 24 to encode bit 2 of imm26
     DCHECK_EQ(0, imm26 & 1);
@@ skipping 4001 matching lines @@
       // Don't record external references unless the heap will be serialized.
       (rmode == RelocInfo::EXTERNAL_REFERENCE && !serializer_enabled() &&
        !emit_debug_code())) {
     return;
   }
   DCHECK(buffer_space() >= kMaxRelocSize);  // too late to grow buffer here
   if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
     data = RecordedAstId().ToInt();
     ClearRecordedAstId();
   }
-  RelocInfo rinfo(isolate(), pc_, rmode, data, NULL);
+  RelocInfo rinfo(pc_, rmode, data, NULL);
   reloc_info_writer.Write(&rinfo);
 }
 
 
 ConstantPoolEntry::Access Assembler::ConstantPoolAddEntry(int position,
                                                           RelocInfo::Mode rmode,
                                                           intptr_t value) {
   DCHECK(rmode != RelocInfo::COMMENT && rmode != RelocInfo::CONST_POOL &&
          rmode != RelocInfo::NONE64);
   bool sharing_ok = RelocInfo::IsNone(rmode) ||
@@ skipping 333 matching lines @@
     instr_at_put(pc, SetVldrDRegisterImmediateOffset(instr, offset));
   } else {
     // Instruction to patch must be 'ldr rd, [pp, #0]'.
     DCHECK((IsLdrPpImmediateOffset(instr) &&
             GetLdrRegisterImmediateOffset(instr) == 0));
     DCHECK(is_uint12(offset));
     instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset));
   }
 }
 
+PatchingAssembler::PatchingAssembler(IsolateData isolate_data, byte* address,
+                                     int instructions)
+    : Assembler(isolate_data, address, instructions * kInstrSize + kGap) {
+  DCHECK_EQ(reloc_info_writer.pos(), buffer_ + buffer_size_);
+}
+
+PatchingAssembler::~PatchingAssembler() {
+  // Check that we don't have any pending constant pools.
+  DCHECK(pending_32_bit_constants_.empty());
+  DCHECK(pending_64_bit_constants_.empty());
+
+  // Check that the code was patched as expected.
+  DCHECK_EQ(pc_, buffer_ + buffer_size_ - kGap);
+  DCHECK_EQ(reloc_info_writer.pos(), buffer_ + buffer_size_);
+}
+
+void PatchingAssembler::Emit(Address addr) {
+  emit(reinterpret_cast<Instr>(addr));
+}
+
+void PatchingAssembler::FlushICache(Isolate* isolate) {
+  Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
+}
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM