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Issue 27301003: Fixed bug in extractps instruction on ia32 and x64 (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 2 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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2340 2340
2341 2341
2342 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { 2342 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2343 ASSERT(IsEnabled(SSE4_1)); 2343 ASSERT(IsEnabled(SSE4_1));
2344 ASSERT(is_uint8(imm8)); 2344 ASSERT(is_uint8(imm8));
2345 EnsureSpace ensure_space(this); 2345 EnsureSpace ensure_space(this);
2346 EMIT(0x66); 2346 EMIT(0x66);
2347 EMIT(0x0F); 2347 EMIT(0x0F);
2348 EMIT(0x3A); 2348 EMIT(0x3A);
2349 EMIT(0x17); 2349 EMIT(0x17);
2350 emit_sse_operand(dst, src); 2350 emit_sse_operand(src, dst);
2351 EMIT(imm8); 2351 EMIT(imm8);
2352 } 2352 }
2353 2353
2354 2354
2355 void Assembler::pand(XMMRegister dst, XMMRegister src) { 2355 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2356 ASSERT(IsEnabled(SSE2)); 2356 ASSERT(IsEnabled(SSE2));
2357 EnsureSpace ensure_space(this); 2357 EnsureSpace ensure_space(this);
2358 EMIT(0x66); 2358 EMIT(0x66);
2359 EMIT(0x0F); 2359 EMIT(0x0F);
2360 EMIT(0xDB); 2360 EMIT(0xDB);
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2479 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { 2479 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2480 EMIT(0xC0 | dst.code() << 3 | src.code()); 2480 EMIT(0xC0 | dst.code() << 3 | src.code());
2481 } 2481 }
2482 2482
2483 2483
2484 void Assembler::emit_sse_operand(Register dst, XMMRegister src) { 2484 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2485 EMIT(0xC0 | dst.code() << 3 | src.code()); 2485 EMIT(0xC0 | dst.code() << 3 | src.code());
2486 } 2486 }
2487 2487
2488 2488
2489 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2490 EMIT(0xC0 | (dst.code() << 3) | src.code());
2491 }
2492
2493
2489 void Assembler::Print() { 2494 void Assembler::Print() {
2490 Disassembler::Decode(isolate(), stdout, buffer_, pc_); 2495 Disassembler::Decode(isolate(), stdout, buffer_, pc_);
2491 } 2496 }
2492 2497
2493 2498
2494 void Assembler::RecordJSReturn() { 2499 void Assembler::RecordJSReturn() {
2495 positions_recorder()->WriteRecordedPositions(); 2500 positions_recorder()->WriteRecordedPositions();
2496 EnsureSpace ensure_space(this); 2501 EnsureSpace ensure_space(this);
2497 RecordRelocInfo(RelocInfo::JS_RETURN); 2502 RecordRelocInfo(RelocInfo::JS_RETURN);
2498 } 2503 }
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2684 fprintf(coverage_log, "%s\n", file_line); 2689 fprintf(coverage_log, "%s\n", file_line);
2685 fflush(coverage_log); 2690 fflush(coverage_log);
2686 } 2691 }
2687 } 2692 }
2688 2693
2689 #endif 2694 #endif
2690 2695
2691 } } // namespace v8::internal 2696 } } // namespace v8::internal
2692 2697
2693 #endif // V8_TARGET_ARCH_IA32 2698 #endif // V8_TARGET_ARCH_IA32
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