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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 2729943002: [WASM] Implement remaining F32x4 operations for ARM. (Closed)
Patch Set: Rebase. Created 3 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 109 matching lines...) Expand 10 before | Expand all | Expand 10 after
120 V(ArmStr) \ 120 V(ArmStr) \
121 V(ArmPush) \ 121 V(ArmPush) \
122 V(ArmPoke) \ 122 V(ArmPoke) \
123 V(ArmFloat32x4Splat) \ 123 V(ArmFloat32x4Splat) \
124 V(ArmFloat32x4ExtractLane) \ 124 V(ArmFloat32x4ExtractLane) \
125 V(ArmFloat32x4ReplaceLane) \ 125 V(ArmFloat32x4ReplaceLane) \
126 V(ArmFloat32x4FromInt32x4) \ 126 V(ArmFloat32x4FromInt32x4) \
127 V(ArmFloat32x4FromUint32x4) \ 127 V(ArmFloat32x4FromUint32x4) \
128 V(ArmFloat32x4Abs) \ 128 V(ArmFloat32x4Abs) \
129 V(ArmFloat32x4Neg) \ 129 V(ArmFloat32x4Neg) \
130 V(ArmFloat32x4RecipApprox) \
131 V(ArmFloat32x4RecipSqrtApprox) \
130 V(ArmFloat32x4Add) \ 132 V(ArmFloat32x4Add) \
131 V(ArmFloat32x4Sub) \ 133 V(ArmFloat32x4Sub) \
134 V(ArmFloat32x4Mul) \
135 V(ArmFloat32x4Min) \
136 V(ArmFloat32x4Max) \
137 V(ArmFloat32x4RecipRefine) \
138 V(ArmFloat32x4RecipSqrtRefine) \
132 V(ArmFloat32x4Equal) \ 139 V(ArmFloat32x4Equal) \
133 V(ArmFloat32x4NotEqual) \ 140 V(ArmFloat32x4NotEqual) \
141 V(ArmFloat32x4LessThan) \
142 V(ArmFloat32x4LessThanOrEqual) \
134 V(ArmInt32x4Splat) \ 143 V(ArmInt32x4Splat) \
135 V(ArmInt32x4ExtractLane) \ 144 V(ArmInt32x4ExtractLane) \
136 V(ArmInt32x4ReplaceLane) \ 145 V(ArmInt32x4ReplaceLane) \
137 V(ArmInt32x4FromFloat32x4) \ 146 V(ArmInt32x4FromFloat32x4) \
138 V(ArmUint32x4FromFloat32x4) \ 147 V(ArmUint32x4FromFloat32x4) \
139 V(ArmInt32x4Neg) \ 148 V(ArmInt32x4Neg) \
140 V(ArmInt32x4ShiftLeftByScalar) \ 149 V(ArmInt32x4ShiftLeftByScalar) \
141 V(ArmInt32x4ShiftRightByScalar) \ 150 V(ArmInt32x4ShiftRightByScalar) \
142 V(ArmInt32x4Add) \ 151 V(ArmInt32x4Add) \
143 V(ArmInt32x4Sub) \ 152 V(ArmInt32x4Sub) \
144 V(ArmInt32x4Mul) \ 153 V(ArmInt32x4Mul) \
145 V(ArmInt32x4Min) \ 154 V(ArmInt32x4Min) \
146 V(ArmInt32x4Max) \ 155 V(ArmInt32x4Max) \
147 V(ArmInt32x4Equal) \ 156 V(ArmInt32x4Equal) \
148 V(ArmInt32x4NotEqual) \ 157 V(ArmInt32x4NotEqual) \
149 V(ArmInt32x4GreaterThan) \ 158 V(ArmInt32x4LessThan) \
150 V(ArmInt32x4GreaterThanOrEqual) \ 159 V(ArmInt32x4LessThanOrEqual) \
151 V(ArmUint32x4ShiftRightByScalar) \ 160 V(ArmUint32x4ShiftRightByScalar) \
152 V(ArmUint32x4Min) \ 161 V(ArmUint32x4Min) \
153 V(ArmUint32x4Max) \ 162 V(ArmUint32x4Max) \
154 V(ArmUint32x4GreaterThan) \ 163 V(ArmUint32x4LessThan) \
155 V(ArmUint32x4GreaterThanOrEqual) \ 164 V(ArmUint32x4LessThanOrEqual) \
156 V(ArmInt16x8Splat) \ 165 V(ArmInt16x8Splat) \
157 V(ArmInt16x8ExtractLane) \ 166 V(ArmInt16x8ExtractLane) \
158 V(ArmInt16x8ReplaceLane) \ 167 V(ArmInt16x8ReplaceLane) \
159 V(ArmInt16x8Neg) \ 168 V(ArmInt16x8Neg) \
160 V(ArmInt16x8ShiftLeftByScalar) \ 169 V(ArmInt16x8ShiftLeftByScalar) \
161 V(ArmInt16x8ShiftRightByScalar) \ 170 V(ArmInt16x8ShiftRightByScalar) \
162 V(ArmInt16x8Add) \ 171 V(ArmInt16x8Add) \
163 V(ArmInt16x8AddSaturate) \ 172 V(ArmInt16x8AddSaturate) \
164 V(ArmInt16x8Sub) \ 173 V(ArmInt16x8Sub) \
165 V(ArmInt16x8SubSaturate) \ 174 V(ArmInt16x8SubSaturate) \
166 V(ArmInt16x8Mul) \ 175 V(ArmInt16x8Mul) \
167 V(ArmInt16x8Min) \ 176 V(ArmInt16x8Min) \
168 V(ArmInt16x8Max) \ 177 V(ArmInt16x8Max) \
169 V(ArmInt16x8Equal) \ 178 V(ArmInt16x8Equal) \
170 V(ArmInt16x8NotEqual) \ 179 V(ArmInt16x8NotEqual) \
171 V(ArmInt16x8GreaterThan) \ 180 V(ArmInt16x8LessThan) \
172 V(ArmInt16x8GreaterThanOrEqual) \ 181 V(ArmInt16x8LessThanOrEqual) \
173 V(ArmUint16x8ShiftRightByScalar) \ 182 V(ArmUint16x8ShiftRightByScalar) \
174 V(ArmUint16x8AddSaturate) \ 183 V(ArmUint16x8AddSaturate) \
175 V(ArmUint16x8SubSaturate) \ 184 V(ArmUint16x8SubSaturate) \
176 V(ArmUint16x8Min) \ 185 V(ArmUint16x8Min) \
177 V(ArmUint16x8Max) \ 186 V(ArmUint16x8Max) \
178 V(ArmUint16x8GreaterThan) \ 187 V(ArmUint16x8LessThan) \
179 V(ArmUint16x8GreaterThanOrEqual) \ 188 V(ArmUint16x8LessThanOrEqual) \
180 V(ArmInt8x16Splat) \ 189 V(ArmInt8x16Splat) \
181 V(ArmInt8x16ExtractLane) \ 190 V(ArmInt8x16ExtractLane) \
182 V(ArmInt8x16ReplaceLane) \ 191 V(ArmInt8x16ReplaceLane) \
183 V(ArmInt8x16Neg) \ 192 V(ArmInt8x16Neg) \
184 V(ArmInt8x16ShiftLeftByScalar) \ 193 V(ArmInt8x16ShiftLeftByScalar) \
185 V(ArmInt8x16ShiftRightByScalar) \ 194 V(ArmInt8x16ShiftRightByScalar) \
186 V(ArmInt8x16Add) \ 195 V(ArmInt8x16Add) \
187 V(ArmInt8x16AddSaturate) \ 196 V(ArmInt8x16AddSaturate) \
188 V(ArmInt8x16Sub) \ 197 V(ArmInt8x16Sub) \
189 V(ArmInt8x16SubSaturate) \ 198 V(ArmInt8x16SubSaturate) \
190 V(ArmInt8x16Mul) \ 199 V(ArmInt8x16Mul) \
191 V(ArmInt8x16Min) \ 200 V(ArmInt8x16Min) \
192 V(ArmInt8x16Max) \ 201 V(ArmInt8x16Max) \
193 V(ArmInt8x16Equal) \ 202 V(ArmInt8x16Equal) \
194 V(ArmInt8x16NotEqual) \ 203 V(ArmInt8x16NotEqual) \
195 V(ArmInt8x16GreaterThan) \ 204 V(ArmInt8x16LessThan) \
196 V(ArmInt8x16GreaterThanOrEqual) \ 205 V(ArmInt8x16LessThanOrEqual) \
197 V(ArmUint8x16ShiftRightByScalar) \ 206 V(ArmUint8x16ShiftRightByScalar) \
198 V(ArmUint8x16AddSaturate) \ 207 V(ArmUint8x16AddSaturate) \
199 V(ArmUint8x16SubSaturate) \ 208 V(ArmUint8x16SubSaturate) \
200 V(ArmUint8x16Min) \ 209 V(ArmUint8x16Min) \
201 V(ArmUint8x16Max) \ 210 V(ArmUint8x16Max) \
202 V(ArmUint8x16GreaterThan) \ 211 V(ArmUint8x16LessThan) \
203 V(ArmUint8x16GreaterThanOrEqual) \ 212 V(ArmUint8x16LessThanOrEqual) \
204 V(ArmSimd128Zero) \ 213 V(ArmSimd128Zero) \
205 V(ArmSimd128And) \ 214 V(ArmSimd128And) \
206 V(ArmSimd128Or) \ 215 V(ArmSimd128Or) \
207 V(ArmSimd128Xor) \ 216 V(ArmSimd128Xor) \
208 V(ArmSimd128Not) \ 217 V(ArmSimd128Not) \
209 V(ArmSimd128Select) \ 218 V(ArmSimd128Select) \
210 V(ArmSimd1x4AnyTrue) \ 219 V(ArmSimd1x4AnyTrue) \
211 V(ArmSimd1x4AllTrue) \ 220 V(ArmSimd1x4AllTrue) \
212 V(ArmSimd1x8AnyTrue) \ 221 V(ArmSimd1x8AnyTrue) \
213 V(ArmSimd1x8AllTrue) \ 222 V(ArmSimd1x8AllTrue) \
(...skipping 16 matching lines...) Expand all
230 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 239 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
231 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 240 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
232 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 241 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
233 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 242 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
234 243
235 } // namespace compiler 244 } // namespace compiler
236 } // namespace internal 245 } // namespace internal
237 } // namespace v8 246 } // namespace v8
238 247
239 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 248 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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