Experimental: periodic merge from the bleeding edge branch to the code...

src/assembler-ia32.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 342 matching lines @@
 //     CpuFeatures::Scope fscope(SSE2);
 //     // Generate SSE2 floating point code.
 //   } else {
 //     // Generate standard x87 floating point code.
 //   }
 class CpuFeatures : public AllStatic {
  public:
   // Feature flags bit positions. They are mostly based on the CPUID spec.
   // (We assign CPUID itself to one of the currently reserved bits --
   // feel free to change this if needed.)
-  enum Feature { SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };
+  enum Feature { SSE3 = 32, SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };
   // Detect features of the target CPU. Set safe defaults if the serializer
   // is enabled (snapshots must be portable).
   static void Probe();
   // Check whether a feature is supported by the target CPU.
-  static bool IsSupported(Feature f) { return supported_ & (1 << f); }
+  static bool IsSupported(Feature f) {
+    return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
+  }
   // Check whether a feature is currently enabled.
-  static bool IsEnabled(Feature f) { return enabled_ & (1 << f); }
+  static bool IsEnabled(Feature f) {
+    return (enabled_ & (static_cast<uint64_t>(1) << f)) != 0;
+  }
   // Enable a specified feature within a scope.
   class Scope BASE_EMBEDDED {
 #ifdef DEBUG
    public:
     explicit Scope(Feature f) {
       ASSERT(CpuFeatures::IsSupported(f));
       old_enabled_ = CpuFeatures::enabled_;
-      CpuFeatures::enabled_ |= (1 << f);
+      CpuFeatures::enabled_ |= (static_cast<uint64_t>(1) << f);
     }
     ~Scope() { CpuFeatures::enabled_ = old_enabled_; }
    private:
-    uint32_t old_enabled_;
+    uint64_t old_enabled_;
 #else
    public:
     explicit Scope(Feature f) {}
 #endif
   };
  private:
-  static uint32_t supported_;
-  static uint32_t enabled_;
+  static uint64_t supported_;
+  static uint64_t enabled_;
 };
 
 
 class Assembler : public Malloced {
  private:
   // The relocation writer's position is kGap bytes below the end of
   // the generated instructions. This leaves enough space for the
   // longest possible ia32 instruction (17 bytes as of 9/26/06) and
   // allows for a single, fast space check per instruction.
   static const int kGap = 32;
@@ skipping 243 matching lines @@
   void fstp_d(const Operand& adr);
 
   void fild_s(const Operand& adr);
   void fild_d(const Operand& adr);
 
   void fist_s(const Operand& adr);
 
   void fistp_s(const Operand& adr);
   void fistp_d(const Operand& adr);
 
+  void fisttp_s(const Operand& adr);
+
   void fabs();
   void fchs();
 
   void fadd(int i);
   void fsub(int i);
   void fmul(int i);
   void fdiv(int i);
 
   void fisub_s(const Operand& adr);
 
   void faddp(int i = 1);
   void fsubp(int i = 1);
   void fsubrp(int i = 1);
   void fmulp(int i = 1);
   void fdivp(int i = 1);
   void fprem();
   void fprem1();
 
   void fxch(int i = 1);
   void fincstp();
   void ffree(int i = 0);
 
   void ftst();
   void fucomp(int i);
   void fucompp();
   void fcompp();
   void fnstsw_ax();
   void fwait();
+  void fnclex();
 
   void frndint();
 
   void sahf();
   void setcc(Condition cc, Register reg);
 
   void cpuid();
 
   // SSE2 instructions
   void cvttss2si(Register dst, const Operand& src);
@@ skipping 155 matching lines @@
  private:
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_ASSEMBLER_IA32_H_