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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_S390_MACRO_ASSEMBLER_S390_H_ | 5 #ifndef V8_S390_MACRO_ASSEMBLER_S390_H_ |
6 #define V8_S390_MACRO_ASSEMBLER_S390_H_ | 6 #define V8_S390_MACRO_ASSEMBLER_S390_H_ |
7 | 7 |
8 #include "src/assembler.h" | 8 #include "src/assembler.h" |
9 #include "src/bailout-reason.h" | 9 #include "src/bailout-reason.h" |
10 #include "src/frames.h" | 10 #include "src/frames.h" |
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335 const Operand& src2); | 335 const Operand& src2); |
336 void Mul64(Register dst, const MemOperand& src1); | 336 void Mul64(Register dst, const MemOperand& src1); |
337 void Mul64(Register dst, Register src1); | 337 void Mul64(Register dst, Register src1); |
338 void Mul64(Register dst, const Operand& src1); | 338 void Mul64(Register dst, const Operand& src1); |
339 void MulPWithCondition(Register dst, Register src1, Register src2); | 339 void MulPWithCondition(Register dst, Register src1, Register src2); |
340 | 340 |
341 // Divide | 341 // Divide |
342 void DivP(Register dividend, Register divider); | 342 void DivP(Register dividend, Register divider); |
343 void Div32(Register dst, Register src1, const MemOperand& src2); | 343 void Div32(Register dst, Register src1, const MemOperand& src2); |
344 void Div32(Register dst, Register src1, Register src2); | 344 void Div32(Register dst, Register src1, Register src2); |
345 void Div32(Register dst, Register src1, const Operand& src2); | |
346 void DivU32(Register dst, Register src1, const MemOperand& src2); | 345 void DivU32(Register dst, Register src1, const MemOperand& src2); |
347 void DivU32(Register dst, Register src1, Register src2); | 346 void DivU32(Register dst, Register src1, Register src2); |
348 void DivU32(Register dst, Register src1, const Operand& src2); | 347 void Div64(Register dst, Register src1, const MemOperand& src2); |
| 348 void Div64(Register dst, Register src1, Register src2); |
| 349 void DivU64(Register dst, Register src1, const MemOperand& src2); |
| 350 void DivU64(Register dst, Register src1, Register src2); |
349 | 351 |
350 // Mod | 352 // Mod |
351 void Mod32(Register dst, Register src1, const MemOperand& src2); | 353 void Mod32(Register dst, Register src1, const MemOperand& src2); |
352 void Mod32(Register dst, Register src1, Register src2); | 354 void Mod32(Register dst, Register src1, Register src2); |
353 void Mod32(Register dst, Register src1, const Operand& src2); | |
354 void ModU32(Register dst, Register src1, const MemOperand& src2); | 355 void ModU32(Register dst, Register src1, const MemOperand& src2); |
355 void ModU32(Register dst, Register src1, Register src2); | 356 void ModU32(Register dst, Register src1, Register src2); |
356 void ModU32(Register dst, Register src1, const Operand& src2); | 357 void Mod64(Register dst, Register src1, const MemOperand& src2); |
| 358 void Mod64(Register dst, Register src1, Register src2); |
| 359 void ModU64(Register dst, Register src1, const MemOperand& src2); |
| 360 void ModU64(Register dst, Register src1, Register src2); |
357 | 361 |
358 // Square root | 362 // Square root |
359 void Sqrt(DoubleRegister result, DoubleRegister input); | 363 void Sqrt(DoubleRegister result, DoubleRegister input); |
360 void Sqrt(DoubleRegister result, const MemOperand& input); | 364 void Sqrt(DoubleRegister result, const MemOperand& input); |
361 | 365 |
362 // Compare | 366 // Compare |
363 void Cmp32(Register src1, Register src2); | 367 void Cmp32(Register src1, Register src2); |
364 void CmpP(Register src1, Register src2); | 368 void CmpP(Register src1, Register src2); |
365 void Cmp32(Register dst, const Operand& opnd); | 369 void Cmp32(Register dst, const Operand& opnd); |
366 void CmpP(Register dst, const Operand& opnd); | 370 void CmpP(Register dst, const Operand& opnd); |
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401 void LoadAndTestP(Register dst, Register src); | 405 void LoadAndTestP(Register dst, Register src); |
402 | 406 |
403 void LoadAndTest32(Register dst, const MemOperand& opnd); | 407 void LoadAndTest32(Register dst, const MemOperand& opnd); |
404 void LoadAndTestP(Register dst, const MemOperand& opnd); | 408 void LoadAndTestP(Register dst, const MemOperand& opnd); |
405 | 409 |
406 // Load Floating Point | 410 // Load Floating Point |
407 void LoadDouble(DoubleRegister dst, const MemOperand& opnd); | 411 void LoadDouble(DoubleRegister dst, const MemOperand& opnd); |
408 void LoadFloat32(DoubleRegister dst, const MemOperand& opnd); | 412 void LoadFloat32(DoubleRegister dst, const MemOperand& opnd); |
409 void LoadFloat32ConvertToDouble(DoubleRegister dst, const MemOperand& mem); | 413 void LoadFloat32ConvertToDouble(DoubleRegister dst, const MemOperand& mem); |
410 | 414 |
| 415 void AddFloat32(DoubleRegister dst, const MemOperand& opnd, |
| 416 DoubleRegister scratch); |
| 417 void AddFloat64(DoubleRegister dst, const MemOperand& opnd, |
| 418 DoubleRegister scratch); |
| 419 void SubFloat32(DoubleRegister dst, const MemOperand& opnd, |
| 420 DoubleRegister scratch); |
| 421 void SubFloat64(DoubleRegister dst, const MemOperand& opnd, |
| 422 DoubleRegister scratch); |
| 423 void MulFloat32(DoubleRegister dst, const MemOperand& opnd, |
| 424 DoubleRegister scratch); |
| 425 void MulFloat64(DoubleRegister dst, const MemOperand& opnd, |
| 426 DoubleRegister scratch); |
| 427 void DivFloat32(DoubleRegister dst, const MemOperand& opnd, |
| 428 DoubleRegister scratch); |
| 429 void DivFloat64(DoubleRegister dst, const MemOperand& opnd, |
| 430 DoubleRegister scratch); |
| 431 void LoadFloat32ToDouble(DoubleRegister dst, const MemOperand& opnd, |
| 432 DoubleRegister scratch); |
| 433 |
411 // Load On Condition | 434 // Load On Condition |
412 void LoadOnConditionP(Condition cond, Register dst, Register src); | 435 void LoadOnConditionP(Condition cond, Register dst, Register src); |
413 | 436 |
414 void LoadPositiveP(Register result, Register input); | 437 void LoadPositiveP(Register result, Register input); |
415 void LoadPositive32(Register result, Register input); | 438 void LoadPositive32(Register result, Register input); |
416 | 439 |
417 // Store Floating Point | 440 // Store Floating Point |
418 void StoreDouble(DoubleRegister dst, const MemOperand& opnd); | 441 void StoreDouble(DoubleRegister dst, const MemOperand& opnd); |
419 void StoreFloat32(DoubleRegister dst, const MemOperand& opnd); | 442 void StoreFloat32(DoubleRegister dst, const MemOperand& opnd); |
420 void StoreDoubleAsFloat32(DoubleRegister src, const MemOperand& mem, | 443 void StoreDoubleAsFloat32(DoubleRegister src, const MemOperand& mem, |
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1838 inline MemOperand NativeContextMemOperand() { | 1861 inline MemOperand NativeContextMemOperand() { |
1839 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX); | 1862 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX); |
1840 } | 1863 } |
1841 | 1864 |
1842 #define ACCESS_MASM(masm) masm-> | 1865 #define ACCESS_MASM(masm) masm-> |
1843 | 1866 |
1844 } // namespace internal | 1867 } // namespace internal |
1845 } // namespace v8 | 1868 } // namespace v8 |
1846 | 1869 |
1847 #endif // V8_S390_MACRO_ASSEMBLER_S390_H_ | 1870 #endif // V8_S390_MACRO_ASSEMBLER_S390_H_ |
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