Add Int32x4 Wasm Simd Binops, compare ops, select

src/compiler/x64/code-generator-x64.cc

Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc
index 8f9b69d2c8b033f7654bbc6f53bd4b5d23934667..c934ed03d558119ae275a41ea395305fa9cc964a 100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -2155,10 +2155,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64Int32x4Splat: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       XMMRegister dst = i.OutputSimd128Register();
       __ Movd(dst, i.InputRegister(0));
-      __ shufps(dst, dst, 0x0);
+      __ Pshufd(dst, dst, 0x0);

[bbudge, 2017/02/27 19:15:03]

This will use AVX if it's available. Are we concerned that we would then be
mixing AVX and SSE instructions (hard coded below)? Is V8 using the VEX prefix
for SSE instructions when AVX is available?

[gdeepti, 2017/02/28 03:36:42]

This will use AVX when available, I noticed that most packed integer
instructions have the AVX version implemented as well, so added this. Removed
now till we have support for all the AVX versions of simd instructions or
consistently use the instructions in the macro-assembler for the switch between
AVX/SSE. 

       break;
     }
     case kX64Int32x4ExtractLane: {
@@ -2177,17 +2176,56 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64Int32x4Add: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       __ paddd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
     case kX64Int32x4Sub: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       __ psubd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
-    case kX64Simd128Zero: {
+    case kX64Int32x4Mul: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pmulld(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Min: {
       CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pminsd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Max: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pmaxsd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Uint32x4Min: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pminud(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Uint32x4Max: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pmaxud(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Equal: {
+      __ pcmpeqd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4NotEqual: {
+      __ pcmpeqd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      __ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
+      __ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
+      break;
+    }
+    case kX64Simd32x4Select: {
+      XMMRegister dst = i.OutputSimd128Register();
+      __ xorps(i.InputSimd128Register(1), i.InputSimd128Register(2));
+      __ andps(dst, i.InputSimd128Register(1));
+      __ xorps(dst, i.InputSimd128Register(2));
+      break;
+    }
+    case kX64Simd128Zero: {
       XMMRegister dst = i.OutputSimd128Register();
       __ xorps(dst, dst);
       break;