| OLD | NEW |
| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ | 5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ |
| 6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ | 6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
| (...skipping 130 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 141 V(X64Dec32) \ | 141 V(X64Dec32) \ |
| 142 V(X64Inc32) \ | 142 V(X64Inc32) \ |
| 143 V(X64Push) \ | 143 V(X64Push) \ |
| 144 V(X64Poke) \ | 144 V(X64Poke) \ |
| 145 V(X64StackCheck) \ | 145 V(X64StackCheck) \ |
| 146 V(X64Int32x4Splat) \ | 146 V(X64Int32x4Splat) \ |
| 147 V(X64Int32x4ExtractLane) \ | 147 V(X64Int32x4ExtractLane) \ |
| 148 V(X64Int32x4ReplaceLane) \ | 148 V(X64Int32x4ReplaceLane) \ |
| 149 V(X64Int32x4Add) \ | 149 V(X64Int32x4Add) \ |
| 150 V(X64Int32x4Sub) \ | 150 V(X64Int32x4Sub) \ |
| 151 V(X64Int32x4Mul) \ |
| 152 V(X64Int32x4Min) \ |
| 153 V(X64Int32x4Max) \ |
| 154 V(X64Int32x4Equal) \ |
| 155 V(X64Int32x4NotEqual) \ |
| 156 V(X64Int32x4ShiftLeftByScalar) \ |
| 157 V(X64Int32x4ShiftRightByScalar) \ |
| 158 V(X64Uint32x4ShiftRightByScalar) \ |
| 159 V(X64Uint32x4Min) \ |
| 160 V(X64Uint32x4Max) \ |
| 161 V(X64Simd32x4Select) \ |
| 151 V(X64Simd128Zero) | 162 V(X64Simd128Zero) |
| 152 | 163 |
| 153 // Addressing modes represent the "shape" of inputs to an instruction. | 164 // Addressing modes represent the "shape" of inputs to an instruction. |
| 154 // Many instructions support multiple addressing modes. Addressing modes | 165 // Many instructions support multiple addressing modes. Addressing modes |
| 155 // are encoded into the InstructionCode of the instruction and tell the | 166 // are encoded into the InstructionCode of the instruction and tell the |
| 156 // code generator after register allocation which assembler method to call. | 167 // code generator after register allocation which assembler method to call. |
| 157 // | 168 // |
| 158 // We use the following local notation for addressing modes: | 169 // We use the following local notation for addressing modes: |
| 159 // | 170 // |
| 160 // M = memory operand | 171 // M = memory operand |
| (...skipping 22 matching lines...) Expand all Loading... |
| 183 V(M8I) /* [ %r2*8 + K] */ \ | 194 V(M8I) /* [ %r2*8 + K] */ \ |
| 184 V(Root) /* [%root + K] */ | 195 V(Root) /* [%root + K] */ |
| 185 | 196 |
| 186 enum X64MemoryProtection { kUnprotected = 0, kProtected = 1 }; | 197 enum X64MemoryProtection { kUnprotected = 0, kProtected = 1 }; |
| 187 | 198 |
| 188 } // namespace compiler | 199 } // namespace compiler |
| 189 } // namespace internal | 200 } // namespace internal |
| 190 } // namespace v8 | 201 } // namespace v8 |
| 191 | 202 |
| 192 #endif // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ | 203 #endif // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ |
| OLD | NEW |