Add Int32x4 Wasm Simd Binops, compare ops, select

src/compiler/x64/code-generator-x64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include <limits>
 
 #include "src/compilation-info.h"
 #include "src/compiler/code-generator-impl.h"
@@ skipping 2125 matching lines @@
     case kX64Poke: {
       int const slot = MiscField::decode(instr->opcode());
       if (HasImmediateInput(instr, 0)) {
         __ movq(Operand(rsp, slot * kPointerSize), i.InputImmediate(0));
       } else {
         __ movq(Operand(rsp, slot * kPointerSize), i.InputRegister(0));
       }
       break;
     }
     case kX64Int32x4Splat: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       XMMRegister dst = i.OutputSimd128Register();
-      __ Movd(dst, i.InputRegister(0));
-      __ shufps(dst, dst, 0x0);
+      __ movd(dst, i.InputRegister(0));
+      __ pshufd(dst, dst, 0x0);
       break;
     }
     case kX64Int32x4ExtractLane: {
       CpuFeatureScope sse_scope(masm(), SSE4_1);
       __ Pextrd(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
       break;
     }
     case kX64Int32x4ReplaceLane: {
       CpuFeatureScope sse_scope(masm(), SSE4_1);
       if (instr->InputAt(2)->IsRegister()) {
         __ Pinsrd(i.OutputSimd128Register(), i.InputRegister(2),
                   i.InputInt8(1));
       } else {
         __ Pinsrd(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
       }
       break;
     }
     case kX64Int32x4Add: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       __ paddd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
     case kX64Int32x4Sub: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       __ psubd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
+    case kX64Int32x4Mul: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);

[bbudge, 2017/03/14 17:50:39]

Do all x64 chips support SSE4.1? This makes me wonder:

http://stackoverflow.com/questions/28185844/do-all-64-bit-intel-architectures...

If not, we should gate IsSimdSupported on this feature, i.e. don't always return
true.

[gdeepti, 2017/03/14 21:32:52]

Summarizing offline discussions, As SupportsSimd128() is vague, changed to
SupportsWasmSimd128(), on x64 and ia32 gated on SSE4_1 support and NEON support
on Arm. 

+      __ pmulld(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Min: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pminsd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Max: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pmaxsd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Uint32x4Min: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pminud(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Uint32x4Max: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      __ pmaxud(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4Equal: {
+      __ pcmpeqd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64Int32x4NotEqual: {
+      __ pcmpeqd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      __ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
+      __ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
+      break;
+    }
+    case kX64Int32x4ShiftLeftByScalar: {
+      __ pslld(i.OutputSimd128Register(), i.InputInt8(1));
+      break;
+    }
+    case kX64Int32x4ShiftRightByScalar: {
+      __ psrad(i.OutputSimd128Register(), i.InputInt8(1));
+      break;
+    }
+    case kX64Uint32x4ShiftRightByScalar: {
+      __ psrld(i.OutputSimd128Register(), i.InputInt8(1));
+      break;
+    }
+    case kX64Simd32x4Select: {
+      // Mask used here is stored in dst.
+      XMMRegister dst = i.OutputSimd128Register();
+      __ movaps(kScratchDoubleReg, i.InputSimd128Register(1));
+      __ xorps(kScratchDoubleReg, i.InputSimd128Register(2));
+      __ andps(dst, kScratchDoubleReg);
+      __ xorps(dst, i.InputSimd128Register(2));
+      break;
+    }
     case kX64Simd128Zero: {
-      CpuFeatureScope sse_scope(masm(), SSE4_1);
       XMMRegister dst = i.OutputSimd128Register();
       __ xorps(dst, dst);
       break;
     }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movsxbl);
       break;
     case kCheckedLoadUint8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movzxbl);
       break;
@@ skipping 690 matching lines @@
     int padding_size = last_lazy_deopt_pc_ + space_needed - current_pc;
     __ Nop(padding_size);
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8