[V8] Rename SIMD Create methods and add initialization operators.

src/compiler/x64/instruction-selector-x64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <algorithm>
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
@@ skipping 2256 matching lines @@
     addressing_mode = kMode_MRI;
   } else {
     inputs[input_count++] = g.UseUniqueRegister(index);
     addressing_mode = kMode_MR1;
   }
   inputs[input_count++] = g.UseUniqueRegister(value);
   InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
   Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
 }
 
-void InstructionSelector::VisitCreateInt32x4(Node* node) {
+void InstructionSelector::VisitInt32x4Splat(Node* node) {
   X64OperandGenerator g(this);
-  Emit(kX64Int32x4Create, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
+  Emit(kX64Int32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
   X64OperandGenerator g(this);
   int32_t lane = OpParameter<int32_t>(node);
   Emit(kX64Int32x4ExtractLane, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
 }
 
 void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) {
   X64OperandGenerator g(this);
   int32_t lane = OpParameter<int32_t>(node);
   Emit(kX64Int32x4ReplaceLane, g.DefineSameAsFirst(node),
        g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
        g.Use(node->InputAt(1)));
 }
 
 void InstructionSelector::VisitInt32x4Add(Node* node) {
   X64OperandGenerator g(this);
   Emit(kX64Int32x4Add, g.DefineSameAsFirst(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
 }
 
 void InstructionSelector::VisitInt32x4Sub(Node* node) {
   X64OperandGenerator g(this);
   Emit(kX64Int32x4Sub, g.DefineSameAsFirst(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
 }
 
+void InstructionSelector::VisitSimd128Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x4Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x8Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x16Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags =
       MachineOperatorBuilder::kWord32ShiftIsSafe |
       MachineOperatorBuilder::kWord32Ctz | MachineOperatorBuilder::kWord64Ctz;
   if (CpuFeatures::IsSupported(POPCNT)) {
     flags |= MachineOperatorBuilder::kWord32Popcnt |
              MachineOperatorBuilder::kWord64Popcnt;
   }
@@ skipping 13 matching lines @@
 // static
 MachineOperatorBuilder::AlignmentRequirements
 InstructionSelector::AlignmentRequirements() {
   return MachineOperatorBuilder::AlignmentRequirements::
       FullUnalignedAccessSupport();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8