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Issue 2718433002: MIPS64: Fix corner case for Word64And(Word64Shr(val,0)) reduction (Closed)
Patch Set: Created 3 years, 10 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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398 if (mleft.right().HasValue()) { 398 if (mleft.right().HasValue()) {
399 // Any shift value can match; int32 shifts use `value % 32`. 399 // Any shift value can match; int32 shifts use `value % 32`.
400 uint32_t lsb = mleft.right().Value() & 0x1f; 400 uint32_t lsb = mleft.right().Value() & 0x1f;
401 401
402 // Ext cannot extract bits past the register size, however since 402 // Ext cannot extract bits past the register size, however since
403 // shifting the original value would have introduced some zeros we can 403 // shifting the original value would have introduced some zeros we can
404 // still use Ext with a smaller mask and the remaining bits will be 404 // still use Ext with a smaller mask and the remaining bits will be
405 // zeros. 405 // zeros.
406 if (lsb + mask_width > 32) mask_width = 32 - lsb; 406 if (lsb + mask_width > 32) mask_width = 32 - lsb;
407 407
408 Emit(kMipsExt, g.DefineAsRegister(node), 408 if (lsb == 0 && mask_width == 32) {
409 g.UseRegister(mleft.left().node()), g.TempImmediate(lsb), 409 Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(mleft.left().node()));
410 g.TempImmediate(mask_width)); 410 } else {
411 Emit(kMipsExt, g.DefineAsRegister(node),
412 g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
413 g.TempImmediate(mask_width));
414 }
411 return; 415 return;
412 } 416 }
413 // Other cases fall through to the normal And operation. 417 // Other cases fall through to the normal And operation.
414 } 418 }
415 } 419 }
416 if (m.right().HasValue()) { 420 if (m.right().HasValue()) {
417 uint32_t mask = m.right().Value(); 421 uint32_t mask = m.right().Value();
418 uint32_t shift = base::bits::CountPopulation32(~mask); 422 uint32_t shift = base::bits::CountPopulation32(~mask);
419 uint32_t msb = base::bits::CountLeadingZeros32(~mask); 423 uint32_t msb = base::bits::CountLeadingZeros32(~mask);
420 if (shift != 0 && shift != 32 && msb + shift == 32) { 424 if (shift != 0 && shift != 32 && msb + shift == 32) {
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1916 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || 1920 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
1917 IsMipsArchVariant(kMips32r2)); 1921 IsMipsArchVariant(kMips32r2));
1918 return MachineOperatorBuilder::AlignmentRequirements:: 1922 return MachineOperatorBuilder::AlignmentRequirements::
1919 NoUnalignedAccessSupport(); 1923 NoUnalignedAccessSupport();
1920 } 1924 }
1921 } 1925 }
1922 1926
1923 } // namespace compiler 1927 } // namespace compiler
1924 } // namespace internal 1928 } // namespace internal
1925 } // namespace v8 1929 } // namespace v8
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