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Issue 2711863002: Implement remaining Boolean SIMD operations on ARM. (Closed)
Patch Set: All Boolean vector tests. Created 3 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 1021 matching lines...) Expand 10 before | Expand all | Expand 10 after
1032 COMPARE(vmin(q15, q0, q8), 1032 COMPARE(vmin(q15, q0, q8),
1033 "f260ef60 vmin.f32 q15, q0, q8"); 1033 "f260ef60 vmin.f32 q15, q0, q8");
1034 COMPARE(vmax(q15, q0, q8), 1034 COMPARE(vmax(q15, q0, q8),
1035 "f240ef60 vmax.f32 q15, q0, q8"); 1035 "f240ef60 vmax.f32 q15, q0, q8");
1036 COMPARE(vmax(NeonS8, q0, q1, q2), 1036 COMPARE(vmax(NeonS8, q0, q1, q2),
1037 "f2020644 vmax.s8 q0, q1, q2"); 1037 "f2020644 vmax.s8 q0, q1, q2");
1038 COMPARE(vmin(NeonU16, q1, q2, q8), 1038 COMPARE(vmin(NeonU16, q1, q2, q8),
1039 "f3142670 vmin.u16 q1, q2, q8"); 1039 "f3142670 vmin.u16 q1, q2, q8");
1040 COMPARE(vmax(NeonS32, q15, q0, q8), 1040 COMPARE(vmax(NeonS32, q15, q0, q8),
1041 "f260e660 vmax.s32 q15, q0, q8"); 1041 "f260e660 vmax.s32 q15, q0, q8");
1042 COMPARE(vpmax(NeonS8, d0, d1, d2),
1043 "f2010a02 vpmax.s8 d0, d1, d2");
1044 COMPARE(vpmin(NeonU16, d1, d2, d8),
1045 "f3121a18 vpmin.u16 d1, d2, d8");
1046 COMPARE(vpmax(NeonS32, d15, d0, d8),
1047 "f220fa08 vpmax.s32 d15, d0, d8");
1042 COMPARE(vadd(q15, q0, q8), 1048 COMPARE(vadd(q15, q0, q8),
1043 "f240ed60 vadd.f32 q15, q0, q8"); 1049 "f240ed60 vadd.f32 q15, q0, q8");
1044 COMPARE(vadd(Neon8, q0, q1, q2), 1050 COMPARE(vadd(Neon8, q0, q1, q2),
1045 "f2020844 vadd.i8 q0, q1, q2"); 1051 "f2020844 vadd.i8 q0, q1, q2");
1046 COMPARE(vadd(Neon16, q1, q2, q8), 1052 COMPARE(vadd(Neon16, q1, q2, q8),
1047 "f2142860 vadd.i16 q1, q2, q8"); 1053 "f2142860 vadd.i16 q1, q2, q8");
1048 COMPARE(vadd(Neon32, q15, q0, q8), 1054 COMPARE(vadd(Neon32, q15, q0, q8),
1049 "f260e860 vadd.i32 q15, q0, q8"); 1055 "f260e860 vadd.i32 q15, q0, q8");
1050 COMPARE(vqadd(NeonU8, q0, q1, q2), 1056 COMPARE(vqadd(NeonU8, q0, q1, q2),
1051 "f3020054 vqadd.u8 q0, q1, q2"); 1057 "f3020054 vqadd.u8 q0, q1, q2");
(...skipping 382 matching lines...) Expand 10 before | Expand all | Expand 10 after
1434 1440
1435 COMPARE(ldrexb(r0, r1), "e1d10f9f ldrexb r0, [r1]"); 1441 COMPARE(ldrexb(r0, r1), "e1d10f9f ldrexb r0, [r1]");
1436 COMPARE(strexb(r0, r1, r2), "e1c20f91 strexb r0, r1, [r2]"); 1442 COMPARE(strexb(r0, r1, r2), "e1c20f91 strexb r0, r1, [r2]");
1437 COMPARE(ldrexh(r0, r1), "e1f10f9f ldrexh r0, [r1]"); 1443 COMPARE(ldrexh(r0, r1), "e1f10f9f ldrexh r0, [r1]");
1438 COMPARE(strexh(r0, r1, r2), "e1e20f91 strexh r0, r1, [r2]"); 1444 COMPARE(strexh(r0, r1, r2), "e1e20f91 strexh r0, r1, [r2]");
1439 COMPARE(ldrex(r0, r1), "e1910f9f ldrex r0, [r1]"); 1445 COMPARE(ldrex(r0, r1), "e1910f9f ldrex r0, [r1]");
1440 COMPARE(strex(r0, r1, r2), "e1820f91 strex r0, r1, [r2]"); 1446 COMPARE(strex(r0, r1, r2), "e1820f91 strex r0, r1, [r2]");
1441 1447
1442 VERIFY_RUN(); 1448 VERIFY_RUN();
1443 } 1449 }
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