Implement remaining Boolean SIMD operations on ARM.

test/cctest/test-macro-assembler-arm.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 138 matching lines @@
 
   typedef struct {
     int32_t i32x4_low[4];
     int32_t i32x4_high[4];
     int32_t i16x8_low[8];
     int32_t i16x8_high[8];
     int32_t i8x16_low[16];
     int32_t i8x16_high[16];
     int32_t f32x4_low[4];
     int32_t f32x4_high[4];
+    int32_t i8x16_low_d[16];
+    int32_t i8x16_high_d[16];
   } T;
   T t;
 
   __ stm(db_w, sp, r4.bit() | r5.bit() | lr.bit());
 
   for (int i = 0; i < 4; i++) {
     __ mov(r4, Operand(i));
     __ vdup(Neon32, q1, r4);
     __ ExtractLane(r5, q1, NeonS32, i);
     __ str(r5, MemOperand(r0, offsetof(T, i32x4_low) + 4 * i));
     SwVfpRegister si = SwVfpRegister::from_code(i);
     __ ExtractLane(si, q1, r4, i);
     __ vstr(si, r0, offsetof(T, f32x4_low) + 4 * i);
   }
 
   for (int i = 0; i < 8; i++) {
     __ mov(r4, Operand(i));
     __ vdup(Neon16, q1, r4);
     __ ExtractLane(r5, q1, NeonS16, i);
     __ str(r5, MemOperand(r0, offsetof(T, i16x8_low) + 4 * i));
   }
 
   for (int i = 0; i < 16; i++) {
     __ mov(r4, Operand(i));
     __ vdup(Neon8, q1, r4);
     __ ExtractLane(r5, q1, NeonS8, i);
     __ str(r5, MemOperand(r0, offsetof(T, i8x16_low) + 4 * i));
   }
 
+  for (int i = 0; i < 8; i++) {
+    __ mov(r4, Operand(i));
+    __ vdup(Neon8, q1, r4);  // q1 = d2,d3
+    __ ExtractLane(r5, d2, NeonS8, i);
+    __ str(r5, MemOperand(r0, offsetof(T, i8x16_low_d) + 4 * i));
+    __ ExtractLane(r5, d3, NeonS8, i);
+    __ str(r5, MemOperand(r0, offsetof(T, i8x16_low_d) + 4 * (i + 8)));
+  }
+
   if (CpuFeatures::IsSupported(VFP32DREGS)) {
     for (int i = 0; i < 4; i++) {
       __ mov(r4, Operand(-i));
       __ vdup(Neon32, q15, r4);
       __ ExtractLane(r5, q15, NeonS32, i);
       __ str(r5, MemOperand(r0, offsetof(T, i32x4_high) + 4 * i));
       SwVfpRegister si = SwVfpRegister::from_code(i);
       __ ExtractLane(si, q15, r4, i);
       __ vstr(si, r0, offsetof(T, f32x4_high) + 4 * i);
     }
 
     for (int i = 0; i < 8; i++) {
       __ mov(r4, Operand(-i));
       __ vdup(Neon16, q15, r4);
       __ ExtractLane(r5, q15, NeonS16, i);
       __ str(r5, MemOperand(r0, offsetof(T, i16x8_high) + 4 * i));
     }
 
     for (int i = 0; i < 16; i++) {
       __ mov(r4, Operand(-i));
       __ vdup(Neon8, q15, r4);
       __ ExtractLane(r5, q15, NeonS8, i);
       __ str(r5, MemOperand(r0, offsetof(T, i8x16_high) + 4 * i));
     }
+
+    for (int i = 0; i < 8; i++) {
+      __ mov(r4, Operand(-i));
+      __ vdup(Neon8, q15, r4);  // q1 = d30,d31
+      __ ExtractLane(r5, d30, NeonS8, i);
+      __ str(r5, MemOperand(r0, offsetof(T, i8x16_high_d) + 4 * i));
+      __ ExtractLane(r5, d31, NeonS8, i);
+      __ str(r5, MemOperand(r0, offsetof(T, i8x16_high_d) + 4 * (i + 8)));
+    }
   }
 
   __ ldm(ia_w, sp, r4.bit() | r5.bit() | pc.bit());
 
   CodeDesc desc;
   masm->GetCode(&desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
 #ifdef DEBUG
   OFStream os(stdout);
   code->Print(os);
 #endif
   F3 f = FUNCTION_CAST<F3>(code->entry());
   Object* dummy = CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0);
   USE(dummy);
   for (int i = 0; i < 4; i++) {
     CHECK_EQ(i, t.i32x4_low[i]);
     CHECK_EQ(i, t.f32x4_low[i]);
   }
   for (int i = 0; i < 8; i++) {
     CHECK_EQ(i, t.i16x8_low[i]);
   }
   for (int i = 0; i < 16; i++) {
     CHECK_EQ(i, t.i8x16_low[i]);
   }
+  for (int i = 0; i < 8; i++) {
+    CHECK_EQ(i, t.i8x16_low_d[i]);
+    CHECK_EQ(i, t.i8x16_low_d[i + 8]);
+  }
   if (CpuFeatures::IsSupported(VFP32DREGS)) {
     for (int i = 0; i < 4; i++) {
       CHECK_EQ(-i, t.i32x4_high[i]);
       CHECK_EQ(-i, t.f32x4_high[i]);
     }
     for (int i = 0; i < 8; i++) {
       CHECK_EQ(-i, t.i16x8_high[i]);
     }
     for (int i = 0; i < 16; i++) {
       CHECK_EQ(-i, t.i8x16_high[i]);
     }
+    for (int i = 0; i < 8; i++) {
+      CHECK_EQ(-i, t.i8x16_high_d[i]);
+      CHECK_EQ(-i, t.i8x16_high_d[i + 8]);
+    }
   }
 }
 
 TEST(ReplaceLane) {
   if (!CpuFeatures::IsSupported(NEON)) return;
 
   // Allocate an executable page of memory.
   size_t actual_size;
   byte* buffer = static_cast<byte*>(v8::base::OS::Allocate(
       Assembler::kMinimalBufferSize, &actual_size, true));
@@ skipping 224 matching lines @@
   CHECK_EQ_32X4(_32x4_1111, 1, 1, 1, 1);
   CHECK_EQ_32X4(_32x4_2222, 2, 2, 2, 2);
   CHECK_EQ_32X4(_32x4_3333, 3, 3, 3, 3);
   CHECK_EQ_32X4(_32x4_2103, 3, 0, 1, 2);
   CHECK_EQ_32X4(_32x4_0321, 1, 2, 3, 0);
   CHECK_EQ_32X4(_32x4_1132, 2, 3, 1, 1);
   CHECK_EQ_32X4(_32x4_1132_in_place, 2, 3, 1, 1);
 }
 
 #undef __