Implement remaining Boolean SIMD operations on ARM.

test/cctest/test-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1209 matching lines @@
            (bit_cast<int64_t>(t.div_result) >> 32) & 0x7fffffff);
   CHECK_EQ(kArmNanLower32, bit_cast<int64_t>(t.div_result) & 0xffffffffu);
 }
 
 #define CHECK_EQ_SPLAT(field, ex) \
   CHECK_EQ(ex, t.field[0]);       \
   CHECK_EQ(ex, t.field[1]);       \
   CHECK_EQ(ex, t.field[2]);       \
   CHECK_EQ(ex, t.field[3]);
 
+#define CHECK_EQ_32X2(field, ex0, ex1) \
+  CHECK_EQ(ex0, t.field[0]);           \
+  CHECK_EQ(ex1, t.field[1]);
+
 #define CHECK_EQ_32X4(field, ex0, ex1, ex2, ex3) \
   CHECK_EQ(ex0, t.field[0]);                     \
   CHECK_EQ(ex1, t.field[1]);                     \
   CHECK_EQ(ex2, t.field[2]);                     \
   CHECK_EQ(ex3, t.field[3]);
 
 #define CHECK_ESTIMATE(expected, tolerance, value) \
   CHECK_LT((expected) - (tolerance), value);       \
   CHECK_GT((expected) + (tolerance), value);
 
@@ skipping 51 matching lines @@
     uint32_t vcvt_u32_f32[4];
     float vcvt_f32_s32[4], vcvt_f32_u32[4];
     uint32_t vdup8[4], vdup16[4], vdup32[4];
     float vabsf[4], vnegf[4];
     uint32_t vabs_s8[4], vabs_s16[4], vabs_s32[4];
     uint32_t vneg_s8[4], vneg_s16[4], vneg_s32[4];
     uint32_t veor[4], vand[4], vorr[4];
     float vdupf[4], vaddf[4], vsubf[4], vmulf[4];
     uint32_t vmin_s8[4], vmin_u16[4], vmin_s32[4];
     uint32_t vmax_s8[4], vmax_u16[4], vmax_s32[4];
+    uint32_t vpmin_s8[2], vpmin_u16[2], vpmin_s32[2];
+    uint32_t vpmax_s8[2], vpmax_u16[2], vpmax_s32[2];
     uint32_t vadd8[4], vadd16[4], vadd32[4];
     uint32_t vqadd_s8[4], vqadd_u16[4], vqadd_s32[4];
     uint32_t vsub8[4], vsub16[4], vsub32[4];
     uint32_t vqsub_u8[4], vqsub_s16[4], vqsub_u32[4];
     uint32_t vmul8[4], vmul16[4], vmul32[4];
     uint32_t vshl8[4], vshl16[4], vshl32[5];
     uint32_t vshr_s8[4], vshr_u16[4], vshr_s32[5];
     uint32_t vceq[4], vceqf[4], vcgef[4], vcgtf[4];
     uint32_t vcge_s8[4], vcge_u16[4], vcge_s32[4];
     uint32_t vcgt_s8[4], vcgt_u16[4], vcgt_s32[4];
@@ skipping 294 matching lines @@
     __ mov(r4, Operand(0xff));
     __ vdup(Neon32, q0, r4);
     __ vdup(Neon8, q1, r4);
     __ vmin(NeonS32, q2, q0, q1);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmin_s32))));
     __ vst1(Neon8, NeonListOperand(q2), NeonMemOperand(r4));
     __ vmax(NeonS32, q2, q0, q1);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmax_s32))));
     __ vst1(Neon8, NeonListOperand(q2), NeonMemOperand(r4));
 
+    // vpmin/vpmax integer.
+    __ mov(r4, Operand(0x03));
+    __ vdup(Neon16, q0, r4);
+    __ vdup(Neon8, q1, r4);
+    __ vpmin(NeonS8, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmin_s8));
+    __ vpmax(NeonS8, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmax_s8));
+    __ mov(r4, Operand(0xffff));
+    __ vdup(Neon32, q0, r4);
+    __ vdup(Neon16, q1, r4);
+    __ vpmin(NeonU16, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmin_u16));
+    __ vpmax(NeonU16, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmax_u16));
+    __ mov(r4, Operand(0xff));
+    __ veor(q0, q0, q0);
+    __ vmov(s0, r4);
+    __ vdup(Neon8, q1, r4);
+    __ vpmin(NeonS32, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmin_s32));
+    __ vpmax(NeonS32, d4, d0, d2);
+    __ vstr(d4, r0, offsetof(T, vpmax_s32));
+
     // vadd (integer).
     __ mov(r4, Operand(0x81));
     __ vdup(Neon8, q0, r4);
     __ mov(r4, Operand(0x82));
     __ vdup(Neon8, q1, r4);
     __ vadd(Neon8, q1, q1, q0);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vadd8))));
     __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
     __ mov(r4, Operand(0x8001));
     __ vdup(Neon16, q0, r4);
@@ skipping 360 matching lines @@
     CHECK_EQ_32X4(vcgtf, 0u, 0xffffffffu, 0u, 0u);
     // [0, 3, 0, 3, ...] and [3, 3, 3, 3, ...]
     CHECK_EQ_SPLAT(vmin_s8, 0x00030003u);
     CHECK_EQ_SPLAT(vmax_s8, 0x03030303u);
     // [0x00ff, 0x00ff, ...] and [0xffff, 0xffff, ...]
     CHECK_EQ_SPLAT(vmin_u16, 0x00ff00ffu);
     CHECK_EQ_SPLAT(vmax_u16, 0xffffffffu);
     // [0x000000ff, 0x000000ff, ...] and [0xffffffff, 0xffffffff, ...]
     CHECK_EQ_SPLAT(vmin_s32, 0xffffffffu);
     CHECK_EQ_SPLAT(vmax_s32, 0xffu);
+    // [0, 3, 0, 3, ...] and [3, 3, 3, 3, ...]
+    CHECK_EQ_32X2(vpmin_s8, 0x00000000u, 0x03030303u);
+    CHECK_EQ_32X2(vpmax_s8, 0x03030303u, 0x03030303u);
+    // [0, ffff, 0, ffff] and [ffff, ffff]
+    CHECK_EQ_32X2(vpmin_u16, 0x00000000u, 0xffffffffu);
+    CHECK_EQ_32X2(vpmax_u16, 0xffffffffu, 0xffffffffu);
+    // [0x000000ff, 0x00000000u] and [0xffffffff, 0xffffffff, ...]
+    CHECK_EQ_32X2(vpmin_s32, 0x00u, 0xffffffffu);
+    CHECK_EQ_32X2(vpmax_s32, 0xffu, 0xffffffffu);
     CHECK_EQ_SPLAT(vadd8, 0x03030303u);
     CHECK_EQ_SPLAT(vadd16, 0x00030003u);
     CHECK_EQ_SPLAT(vadd32, 0x00000003u);
     CHECK_EQ_SPLAT(vqadd_s8, 0x80808080u);
     CHECK_EQ_SPLAT(vqadd_u16, 0xffffffffu);
     CHECK_EQ_SPLAT(vqadd_s32, 0x80000000u);
     CHECK_EQ_SPLAT(vqsub_u8, 0x00000000u);
     CHECK_EQ_SPLAT(vqsub_s16, 0x7fff7fffu);
     CHECK_EQ_SPLAT(vqsub_u32, 0x00000000u);
     CHECK_EQ_SPLAT(vsub8, 0xfefefefeu);
@@ skipping 1720 matching lines @@
   HandleScope scope(isolate);
 
   Assembler assm(isolate, NULL, 0);
   __ mov(r0, Operand(isolate->factory()->infinity_value()));
   __ BlockConstPoolFor(1019);
   for (int i = 0; i < 1019; ++i) __ nop();
   __ vldr(d0, MemOperand(r0, 0));
 }
 
 #undef __