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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 2711863002: Implement remaining Boolean SIMD operations on ARM. (Closed)
Patch Set: Fix macro assembler test. Created 3 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 188 matching lines...) Expand 10 before | Expand all | Expand 10 after
199 V(ArmUint8x16SubSaturate) \ 199 V(ArmUint8x16SubSaturate) \
200 V(ArmUint8x16Min) \ 200 V(ArmUint8x16Min) \
201 V(ArmUint8x16Max) \ 201 V(ArmUint8x16Max) \
202 V(ArmUint8x16GreaterThan) \ 202 V(ArmUint8x16GreaterThan) \
203 V(ArmUint8x16GreaterThanOrEqual) \ 203 V(ArmUint8x16GreaterThanOrEqual) \
204 V(ArmSimd128Zero) \ 204 V(ArmSimd128Zero) \
205 V(ArmSimd128And) \ 205 V(ArmSimd128And) \
206 V(ArmSimd128Or) \ 206 V(ArmSimd128Or) \
207 V(ArmSimd128Xor) \ 207 V(ArmSimd128Xor) \
208 V(ArmSimd128Not) \ 208 V(ArmSimd128Not) \
209 V(ArmSimd32x4Select) \ 209 V(ArmSimd128Select) \
210 V(ArmSimd16x8Select) \ 210 V(ArmSimd1x4AnyTrue) \
211 V(ArmSimd8x16Select) 211 V(ArmSimd1x4AllTrue) \
212 V(ArmSimd1x8AnyTrue) \
213 V(ArmSimd1x8AllTrue) \
214 V(ArmSimd1x16AnyTrue) \
215 V(ArmSimd1x16AllTrue)
212 216
213 // Addressing modes represent the "shape" of inputs to an instruction. 217 // Addressing modes represent the "shape" of inputs to an instruction.
214 // Many instructions support multiple addressing modes. Addressing modes 218 // Many instructions support multiple addressing modes. Addressing modes
215 // are encoded into the InstructionCode of the instruction and tell the 219 // are encoded into the InstructionCode of the instruction and tell the
216 // code generator after register allocation which assembler method to call. 220 // code generator after register allocation which assembler method to call.
217 #define TARGET_ADDRESSING_MODE_LIST(V) \ 221 #define TARGET_ADDRESSING_MODE_LIST(V) \
218 V(Offset_RI) /* [%r0 + K] */ \ 222 V(Offset_RI) /* [%r0 + K] */ \
219 V(Offset_RR) /* [%r0 + %r1] */ \ 223 V(Offset_RR) /* [%r0 + %r1] */ \
220 V(Operand2_I) /* K */ \ 224 V(Operand2_I) /* K */ \
221 V(Operand2_R) /* %r0 */ \ 225 V(Operand2_R) /* %r0 */ \
222 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 226 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
223 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 227 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
224 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 228 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
225 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 229 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
226 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 230 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
227 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 231 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
228 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 232 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
229 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 233 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
230 234
231 } // namespace compiler 235 } // namespace compiler
232 } // namespace internal 236 } // namespace internal
233 } // namespace v8 237 } // namespace v8
234 238
235 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 239 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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