Implement remaining Boolean SIMD operations on ARM.

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 400 matching lines @@
 const QwNeonRegister q13 = { 13 };
 const QwNeonRegister q14 = { 14 };
 const QwNeonRegister q15 = { 15 };
 
 
 // Aliases for double registers.  Defined using #define instead of
 // "static const DwVfpRegister&" because Clang complains otherwise when a
 // compilation unit that includes this header doesn't use the variables.
 #define kFirstCalleeSavedDoubleReg d8
 #define kLastCalleeSavedDoubleReg d15
-// kDoubleRegZero and kScratchDoubleReg must pair to form kScratchQuadReg.
+// kDoubleRegZero and kScratchDoubleReg must pair to form kScratchQuadReg. SIMD
+// code depends on kDoubleRegZero before kScratchDoubleReg.
 #define kDoubleRegZero d14
 #define kScratchDoubleReg d15
 // After using kScratchQuadReg, kDoubleRegZero must be reset to 0.
 #define kScratchQuadReg q7
 
 // Coprocessor register
 struct CRegister {
   bool is_valid() const { return 0 <= reg_code && reg_code < 16; }
   bool is(CRegister creg) const { return reg_code == creg.reg_code; }
   int code() const {
@@ skipping 920 matching lines @@
   void vmul(QwNeonRegister dst, QwNeonRegister src1,
             QwNeonRegister src2);
   void vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
             QwNeonRegister src2);
   void vmin(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vmin(NeonDataType dt, QwNeonRegister dst,
             QwNeonRegister src1, QwNeonRegister src2);
   void vmax(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vmax(NeonDataType dt, QwNeonRegister dst,
             QwNeonRegister src1, QwNeonRegister src2);
+  void vpmin(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
+             DwVfpRegister src2);
+  void vpmax(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
+             DwVfpRegister src2);
   void vshl(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src, int shift);
   void vshr(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src, int shift);
   // vrecpe and vrsqrte only support floating point lanes.
   void vrecpe(QwNeonRegister dst, QwNeonRegister src);
   void vrsqrte(QwNeonRegister dst, QwNeonRegister src);
   void vrecps(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vrsqrts(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
             QwNeonRegister src2);
   void vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
@@ skipping 413 matching lines @@
 class EnsureSpace BASE_EMBEDDED {
  public:
   INLINE(explicit EnsureSpace(Assembler* assembler));
 };
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_