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Side by Side Diff: src/arm64/constants-arm64.h

Issue 2711473002: [Atomics] Implement ldaxr/stlxr instructions in ARM64 simulator (Closed)
Patch Set: [Atomics] Implement ldaxr/stlxr instructions in ARM64 simulator Created 3 years, 9 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_ 5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
6 #define V8_ARM64_CONSTANTS_ARM64_H_ 6 #define V8_ARM64_CONSTANTS_ARM64_H_
7 7
8 #include "src/base/macros.h" 8 #include "src/base/macros.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 10
(...skipping 181 matching lines...) Expand 10 before | Expand all | Expand 10 after
192 V_(ImmHint, 11, 5, Bits) \ 192 V_(ImmHint, 11, 5, Bits) \
193 V_(ImmBarrierDomain, 11, 10, Bits) \ 193 V_(ImmBarrierDomain, 11, 10, Bits) \
194 V_(ImmBarrierType, 9, 8, Bits) \ 194 V_(ImmBarrierType, 9, 8, Bits) \
195 \ 195 \
196 /* System (MRS, MSR) */ \ 196 /* System (MRS, MSR) */ \
197 V_(ImmSystemRegister, 19, 5, Bits) \ 197 V_(ImmSystemRegister, 19, 5, Bits) \
198 V_(SysO0, 19, 19, Bits) \ 198 V_(SysO0, 19, 19, Bits) \
199 V_(SysOp1, 18, 16, Bits) \ 199 V_(SysOp1, 18, 16, Bits) \
200 V_(SysOp2, 7, 5, Bits) \ 200 V_(SysOp2, 7, 5, Bits) \
201 V_(CRn, 15, 12, Bits) \ 201 V_(CRn, 15, 12, Bits) \
202 V_(CRm, 11, 8, Bits) 202 V_(CRm, 11, 8, Bits) \
203 \
204 /* Load-/store-exclusive */ \
205 V_(LoadStoreXLoad, 22, 22, Bits) \
206 V_(LoadStoreXNotExclusive, 23, 23, Bits) \
207 V_(LoadStoreXAcquireRelease, 15, 15, Bits) \
208 V_(LoadStoreXSizeLog2, 31, 30, Bits) \
209 V_(LoadStoreXPair, 21, 21, Bits)
203 210
204 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 211 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
205 /* NZCV */ \ 212 /* NZCV */ \
206 V_(Flags, 31, 28, Bits, uint32_t) \ 213 V_(Flags, 31, 28, Bits, uint32_t) \
207 V_(N, 31, 31, Bits, bool) \ 214 V_(N, 31, 31, Bits, bool) \
208 V_(Z, 30, 30, Bits, bool) \ 215 V_(Z, 30, 30, Bits, bool) \
209 V_(C, 29, 29, Bits, bool) \ 216 V_(C, 29, 29, Bits, bool) \
210 V_(V, 28, 28, Bits, uint32_t) \ 217 V_(V, 28, 28, Bits, uint32_t) \
211 M_(NZCV, Flags_mask) \ 218 M_(NZCV, Flags_mask) \
212 \ 219 \
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1250 1257
1251 enum UnallocatedOp { 1258 enum UnallocatedOp {
1252 UnallocatedFixed = 0x00000000, 1259 UnallocatedFixed = 0x00000000,
1253 UnallocatedFMask = 0x00000000 1260 UnallocatedFMask = 0x00000000
1254 }; 1261 };
1255 1262
1256 } // namespace internal 1263 } // namespace internal
1257 } // namespace v8 1264 } // namespace v8
1258 1265
1259 #endif // V8_ARM64_CONSTANTS_ARM64_H_ 1266 #endif // V8_ARM64_CONSTANTS_ARM64_H_
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