PPC: Add OPCODE_LIST macro

src/ppc/disasm-ppc.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 353 matching lines @@
 // UnknownFormat(instr) which will just print opcode name of the
 // instruction bits.
 void Decoder::UnknownFormat(Instruction* instr, const char* name) {
   char buffer[100];
   snprintf(buffer, sizeof(buffer), "%s (unknown-format)", name);
   Format(instr, buffer);
 }
 
 
 void Decoder::DecodeExt1(Instruction* instr) {
-  switch (instr->Bits(10, 1) << 1) {
+  switch (EXT1 | (instr->BitField(10, 1))) {
     case MCRF: {
       UnknownFormat(instr, "mcrf");  // not used by V8
       break;
     }
     case BCLRX: {
-      int bo = instr->Bits(25, 21) << 21;
+      int bo = instr->BitField(25, 21);
       int bi = instr->Bits(20, 16);
       CRBit cond = static_cast<CRBit>(bi & (CRWIDTH - 1));
       switch (bo) {
         case DCBNZF: {
           UnknownFormat(instr, "bclrx-dcbnzf");
           break;
         }
         case DCBEZF: {
           UnknownFormat(instr, "bclrx-dcbezf");
           break;
@@ skipping 49 matching lines @@
           break;
         }
         case BA: {
           Format(instr, "blr'l");
           break;
         }
       }
       break;
     }
     case BCCTRX: {
-      switch (instr->Bits(25, 21) << 21) {
+      switch (instr->BitField(25, 21)) {
         case DCBNZF: {
           UnknownFormat(instr, "bcctrx-dcbnzf");
           break;
         }
         case DCBEZF: {
           UnknownFormat(instr, "bcctrx-dcbezf");
           break;
         }
         case BF: {
           UnknownFormat(instr, "bcctrx-bf");
@@ skipping 73 matching lines @@
     }
     default: {
       Unknown(instr);  // not used by V8
     }
   }
 }
 
 
 void Decoder::DecodeExt2(Instruction* instr) {
   // Some encodings are 10-1 bits, handle those first
-  switch (instr->Bits(10, 1) << 1) {
+  switch (EXT2 | (instr->BitField(10, 1))) {
     case SRWX: {
       Format(instr, "srw'.    'ra, 'rs, 'rb");
       return;
     }
 #if V8_TARGET_ARCH_PPC64
     case SRDX: {
       Format(instr, "srd'.    'ra, 'rs, 'rb");
       return;
     }
 #endif
@@ skipping 80 matching lines @@
       return;
     }
 #if V8_TARGET_ARCH_PPC64
     case POPCNTD: {
       Format(instr, "popcntd  'ra, 'rs");
       return;
     }
 #endif
   }
 
-  switch (instr->Bits(10, 2) << 2) {
+  switch (EXT2 | (instr->BitField(10, 2))) {
     case SRADIX: {
       Format(instr, "sradi'.  'ra,'rs,'sh");
       return;
     }
   }
 
   // ?? are all of these xo_form?
-  switch (instr->Bits(9, 1) << 1) {
+  switch (EXT2 | (instr->BitField(9, 1))) {
     case CMP: {
 #if V8_TARGET_ARCH_PPC64
       if (instr->Bit(21)) {
 #endif
         Format(instr, "cmp     'ra, 'rb");
 #if V8_TARGET_ARCH_PPC64
       } else {
         Format(instr, "cmpw    'ra, 'rb");
       }
 #endif
@@ skipping 228 matching lines @@
       Format(instr, "mtfprwa 'Dt, 'ra");
       return;
     }
     case MTVSRWZ: {
       Format(instr, "mtfprwz 'Dt, 'ra");
       return;
     }
 #endif
   }
 
-  switch (instr->Bits(5, 1) << 1) {
+  switch (EXT2 | (instr->BitField(5, 1))) {
     case ISEL: {
       Format(instr, "isel    'rt, 'ra, 'rb");
       return;
     }
     default: {
       Unknown(instr);  // not used by V8
     }
   }
 }
 
 
 void Decoder::DecodeExt3(Instruction* instr) {
-  switch (instr->Bits(10, 1) << 1) {
+  switch (EXT3 | (instr->BitField(10, 1))) {
     case FCFID: {
       Format(instr, "fcfids'. 'Dt, 'Db");
       break;
     }
     case FCFIDU: {
       Format(instr, "fcfidus'.'Dt, 'Db");
       break;
     }
     default: {
       Unknown(instr);  // not used by V8
     }
   }
 }
 
 
 void Decoder::DecodeExt4(Instruction* instr) {
-  switch (instr->Bits(5, 1) << 1) {
+  switch (EXT4 | (instr->BitField(5, 1))) {
     case FDIV: {
       Format(instr, "fdiv'.   'Dt, 'Da, 'Db");
       return;
     }
     case FSUB: {
       Format(instr, "fsub'.   'Dt, 'Da, 'Db");
       return;
     }
     case FADD: {
       Format(instr, "fadd'.   'Dt, 'Da, 'Db");
@@ skipping 14 matching lines @@
     case FMSUB: {
       Format(instr, "fmsub'.  'Dt, 'Da, 'Dc, 'Db");
       return;
     }
     case FMADD: {
       Format(instr, "fmadd'.  'Dt, 'Da, 'Dc, 'Db");
       return;
     }
   }
 
-  switch (instr->Bits(10, 1) << 1) {
+  switch (EXT4 | (instr->BitField(10, 1))) {
     case FCMPU: {
       Format(instr, "fcmpu   'Da, 'Db");
       break;
     }
     case FRSP: {
       Format(instr, "frsp'.   'Dt, 'Db");
       break;
     }
     case FCFID: {
       Format(instr, "fcfid'.  'Dt, 'Db");
@@ skipping 80 matching lines @@
       break;
     }
     default: {
       Unknown(instr);  // not used by V8
     }
   }
 }
 
 
 void Decoder::DecodeExt5(Instruction* instr) {
-  switch (instr->Bits(4, 2) << 2) {
+  switch (EXT5 | (instr->BitField(4, 2))) {
     case RLDICL: {
       Format(instr, "rldicl'. 'ra, 'rs, 'sh, 'mb");
       return;
     }
     case RLDICR: {
       Format(instr, "rldicr'. 'ra, 'rs, 'sh, 'me");
       return;
     }
     case RLDIC: {
       Format(instr, "rldic'.  'ra, 'rs, 'sh, 'mb");
       return;
     }
     case RLDIMI: {
       Format(instr, "rldimi'. 'ra, 'rs, 'sh, 'mb");
       return;
     }
   }
-  switch (instr->Bits(4, 1) << 1) {
+  switch (EXT5 | (instr->BitField(4, 1))) {
     case RLDCL: {
       Format(instr, "rldcl'.  'ra, 'rs, 'sb, 'mb");
       return;
     }
   }
   Unknown(instr);  // not used by V8
 }
 
 void Decoder::DecodeExt6(Instruction* instr) {
-  switch (instr->Bits(10, 3) << 3) {
+  switch (EXT6 | (instr->BitField(10, 3))) {
 #define DECODE_XX3_INSTRUCTIONS(name, opcode_name, opcode_value) \
   case opcode_name: {                                            \
     Format(instr, #name" 'Dt, 'Da, 'Db");                        \
     return;                                                      \
   }
-    XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
+    PPC_XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
 #undef DECODE_XX3_INSTRUCTIONS
   }
-  switch (instr->Bits(10, 2) << 2) {
+  switch (EXT6 | (instr->BitField(10, 2))) {
 #define DECODE_XX2_INSTRUCTIONS(name, opcode_name, opcode_value) \
   case opcode_name: {                                            \
     Format(instr, #name" 'Dt, 'Db");                             \
     return;                                                      \
   }
-    XX2_OPCODE_LIST(DECODE_XX2_INSTRUCTIONS)
+    PPC_XX2_OPCODE_LIST(DECODE_XX2_INSTRUCTIONS)
   }
 #undef DECODE_XX3_INSTRUCTIONS
   Unknown(instr);  // not used by V8
 }
 
 #undef VERIFIY
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
 int Decoder::InstructionDecode(byte* instr_ptr) {
   Instruction* instr = Instruction::At(instr_ptr);
   // Print raw instruction bytes.
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%08x       ",
                               instr->InstructionBits());
 
   if (ABI_USES_FUNCTION_DESCRIPTORS && instr->InstructionBits() == 0) {
     // The first field will be identified as a jump table entry.  We
     // emit the rest of the structure as zero, so just skip past them.
     Format(instr, "constant");
     return Instruction::kInstrSize;
   }
 
-  switch (instr->OpcodeValue() << 26) {
+  uint32_t opcode = instr->OpcodeValue() << 26;
+  switch (opcode) {
     case TWI: {
       PrintSoftwareInterrupt(instr->SvcValue());
       break;
     }
     case MULLI: {
       UnknownFormat(instr, "mulli");
       break;
     }
     case SUBFIC: {
       Format(instr, "subfic  'rt, 'ra, 'int16");
@@ skipping 365 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_PPC