Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(9)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: test/NaCl/Bitcode/vector.ll

Issue 270723003: PNaCl SIMD: allow the bitcode reader to read select instructions properly (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master
Patch Set: Created 6 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp ('k') | test/NaCl/PNaClABI/instructions.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 ; Tests that vector operations survive through PNaCl bitcode files. 1 ; Tests that vector operations survive through PNaCl bitcode files.
2 2
3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \ 3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \
4 ; RUN: | FileCheck %s 4 ; RUN: | FileCheck %s
5 5
6 define internal void @binops() { ; CHECK-LABEL: binops 6 define internal void @binops() { ; CHECK-LABEL: binops
7 %1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, un def 7 %1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, un def
8 %2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef, undef 8 %2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef, undef
9 %3 = sub <4 x i32> undef, undef ; CHECK-NEXT: %3 = sub <4 x i32> undef, un def 9 %3 = sub <4 x i32> undef, undef ; CHECK-NEXT: %3 = sub <4 x i32> undef, un def
10 %4 = fsub <4 x float> undef, undef ; CHECK-NEXT: %4 = fsub <4 x float> undef, undef 10 %4 = fsub <4 x float> undef, undef ; CHECK-NEXT: %4 = fsub <4 x float> undef, undef
11 %5 = mul <4 x i32> undef, undef ; CHECK-NEXT: %5 = mul <4 x i32> undef, un def 11 %5 = mul <4 x i32> undef, undef ; CHECK-NEXT: %5 = mul <4 x i32> undef, un def
12 %6 = fmul <4 x float> undef, undef ; CHECK-NEXT: %6 = fmul <4 x float> undef, undef 12 %6 = fmul <4 x float> undef, undef ; CHECK-NEXT: %6 = fmul <4 x float> undef, undef
13 %7 = udiv <4 x i32> undef, undef ; CHECK-NEXT: %7 = udiv <4 x i32> undef, u ndef 13 %7 = udiv <4 x i32> undef, undef ; CHECK-NEXT: %7 = udiv <4 x i32> undef, u ndef
14 %8 = sdiv <4 x i32> undef, undef ; CHECK-NEXT: %8 = sdiv <4 x i32> undef, u ndef 14 %8 = sdiv <4 x i32> undef, undef ; CHECK-NEXT: %8 = sdiv <4 x i32> undef, u ndef
15 %9 = fdiv <4 x float> undef, undef ; CHECK-NEXT: %9 = fdiv <4 x float> undef, undef 15 %9 = fdiv <4 x float> undef, undef ; CHECK-NEXT: %9 = fdiv <4 x float> undef, undef
16 %10 = urem <4 x i32> undef, undef ; CHECK-NEXT: %10 = urem <4 x i32> undef, undef 16 %10 = urem <4 x i32> undef, undef ; CHECK-NEXT: %10 = urem <4 x i32> undef, undef
17 %11 = srem <4 x i32> undef, undef ; CHECK-NEXT: %11 = srem <4 x i32> undef, undef 17 %11 = srem <4 x i32> undef, undef ; CHECK-NEXT: %11 = srem <4 x i32> undef, undef
18 %12 = frem <4 x float> undef, undef ; CHECK-NEXT: %12 = frem <4 x float> undef , undef 18 %12 = frem <4 x float> undef, undef ; CHECK-NEXT: %12 = frem <4 x float> undef , undef
19 %13 = shl <4 x i32> undef, undef ; CHECK-NEXT: %13 = shl <4 x i32> undef, u ndef 19 %13 = shl <4 x i32> undef, undef ; CHECK-NEXT: %13 = shl <4 x i32> undef, u ndef
20 %14 = lshr <4 x i32> undef, undef ; CHECK-NEXT: %14 = lshr <4 x i32> undef, undef 20 %14 = lshr <4 x i32> undef, undef ; CHECK-NEXT: %14 = lshr <4 x i32> undef, undef
21 %15 = ashr <4 x i32> undef, undef ; CHECK-NEXT: %15 = ashr <4 x i32> undef, undef 21 %15 = ashr <4 x i32> undef, undef ; CHECK-NEXT: %15 = ashr <4 x i32> undef, undef
22 %16 = and <4 x i32> undef, undef ; CHECK-NEXT: %16 = and <4 x i32> undef, u ndef 22 %16 = and <4 x i32> undef, undef ; CHECK-NEXT: %16 = and <4 x i32> undef, u ndef
23 %17 = or <4 x i32> undef, undef ; CHECK-NEXT: %17 = or <4 x i32> undef, un def 23 %17 = or <4 x i32> undef, undef ; CHECK-NEXT: %17 = or <4 x i32> undef, un def
24 %18 = xor <4 x i32> undef, undef ; CHECK-NEXT: %18 = xor <4 x i32> undef, u ndef 24 %18 = xor <4 x i32> undef, undef ; CHECK-NEXT: %18 = xor <4 x i32> undef, u ndef
25 %19 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef ; CHECK-NEXT: %1 9 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef
25 ret void ; CHECK-NEXT: ret void 26 ret void ; CHECK-NEXT: ret void
26 } 27 }
27 28
28 define internal void @insert_extract() { ; CHECK-LABEL: insert_extract 29 define internal void @insert_extract() { ; CHECK-LABEL: insert_extract
29 %1 = extractelement <4 x i32> undef, i32 0 ; CHECK-NEXT: %1 = extractele ment <4 x i32> undef, i32 0 30 %1 = extractelement <4 x i32> undef, i32 0 ; CHECK-NEXT: %1 = extractele ment <4 x i32> undef, i32 0
30 %2 = extractelement <4 x i32> undef, i32 1 ; CHECK-NEXT: %2 = extractele ment <4 x i32> undef, i32 1 31 %2 = extractelement <4 x i32> undef, i32 1 ; CHECK-NEXT: %2 = extractele ment <4 x i32> undef, i32 1
31 %3 = extractelement <4 x i32> undef, i32 2 ; CHECK-NEXT: %3 = extractele ment <4 x i32> undef, i32 2 32 %3 = extractelement <4 x i32> undef, i32 2 ; CHECK-NEXT: %3 = extractele ment <4 x i32> undef, i32 2
32 %4 = extractelement <4 x i32> undef, i32 3 ; CHECK-NEXT: %4 = extractele ment <4 x i32> undef, i32 3 33 %4 = extractelement <4 x i32> undef, i32 3 ; CHECK-NEXT: %4 = extractele ment <4 x i32> undef, i32 3
33 %5 = insertelement <4 x i32> undef, i32 1, i32 0 ; CHECK-NEXT: %5 = insertelem ent <4 x i32> undef, i32 1, i32 0 34 %5 = insertelement <4 x i32> undef, i32 1, i32 0 ; CHECK-NEXT: %5 = insertelem ent <4 x i32> undef, i32 1, i32 0
34 %6 = insertelement <4 x i32> undef, i32 1, i32 1 ; CHECK-NEXT: %6 = insertelem ent <4 x i32> undef, i32 1, i32 1 35 %6 = insertelement <4 x i32> undef, i32 1, i32 1 ; CHECK-NEXT: %6 = insertelem ent <4 x i32> undef, i32 1, i32 1
35 %7 = insertelement <4 x i32> undef, i32 1, i32 2 ; CHECK-NEXT: %7 = insertelem ent <4 x i32> undef, i32 1, i32 2 36 %7 = insertelement <4 x i32> undef, i32 1, i32 2 ; CHECK-NEXT: %7 = insertelem ent <4 x i32> undef, i32 1, i32 2
36 %8 = insertelement <4 x i32> undef, i32 1, i32 3 ; CHECK-NEXT: %8 = insertelem ent <4 x i32> undef, i32 1, i32 3 37 %8 = insertelement <4 x i32> undef, i32 1, i32 3 ; CHECK-NEXT: %8 = insertelem ent <4 x i32> undef, i32 1, i32 3
37 ret void ; CHECK-NEXT: ret void 38 ret void ; CHECK-NEXT: ret void
38 } 39 }
OLDNEW
« no previous file with comments | « lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp ('k') | test/NaCl/PNaClABI/instructions.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698