[V8] Implement remaining SIMD operations on ARM.

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index ca0174569dd662bd3af7853357b2401b5e8f593f..8b99f4629e42baa35e6c163ba53655c39446b256 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -1615,6 +1615,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmSimd1x4AnyTrue: {
+      break;
+    }
+    case kArmSimd1x4AllTrue: {
+      break;
+    }
     case kArmInt32x4Equal: {
       __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1682,6 +1688,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmSimd1x8AnyTrue: {
+      break;
+    }
+    case kArmSimd1x8AllTrue: {
+      break;
+    }
     case kArmInt16x8ShiftLeftByScalar: {
       __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt4(1));
@@ -1804,6 +1816,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmSimd1x16AnyTrue: {
+      break;
+    }
+    case kArmSimd1x16AllTrue: {
+      break;
+    }
     case kArmInt8x16ShiftLeftByScalar: {
       __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt3(1));
@@ -1926,26 +1944,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kArmSimd32x4Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
-    }
-    case kArmSimd16x8Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
-    }
-    case kArmSimd8x16Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
+    case kArmSimd128Select: {
+      // vbsl clobbers the mask input so make sure it was DefineSameAsFirst.
+      DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
       __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
               i.InputSimd128Register(2));
       break;