[V8] Implement remaining SIMD operations on ARM.

src/compiler/arm/code-generator-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm/macro-assembler-arm.h"
 #include "src/compilation-info.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
@@ skipping 1597 matching lines @@
     case kArmInt32x4Min: {
       __ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
     case kArmInt32x4Max: {
       __ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
+    case kArmSimd1x4AnyTrue: {
+      break;
+    }
+    case kArmSimd1x4AllTrue: {
+      break;
+    }
     case kArmInt32x4Equal: {
       __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
     case kArmInt32x4NotEqual: {
       Simd128Register dst = i.OutputSimd128Register();
       __ vceq(Neon32, dst, i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       __ vmvn(dst, dst);
@@ skipping 47 matching lines @@
     }
     case kArmInt16x8ReplaceLane: {
       __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0),
                      i.InputRegister(2), NeonS16, i.InputInt8(1));
       break;
     }
     case kArmInt16x8Neg: {
       __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmSimd1x8AnyTrue: {
+      break;
+    }
+    case kArmSimd1x8AllTrue: {
+      break;
+    }
     case kArmInt16x8ShiftLeftByScalar: {
       __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt4(1));
       break;
     }
     case kArmInt16x8ShiftRightByScalar: {
       __ vshr(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt4(1));
       break;
     }
@@ skipping 102 matching lines @@
     }
     case kArmInt8x16ReplaceLane: {
       __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0),
                      i.InputRegister(2), NeonS8, i.InputInt8(1));
       break;
     }
     case kArmInt8x16Neg: {
       __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmSimd1x16AnyTrue: {
+      break;
+    }
+    case kArmSimd1x16AllTrue: {
+      break;
+    }
     case kArmInt8x16ShiftLeftByScalar: {
       __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt3(1));
       break;
     }
     case kArmInt8x16ShiftRightByScalar: {
       __ vshr(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputInt3(1));
       break;
     }
@@ skipping 102 matching lines @@
     }
     case kArmSimd128Xor: {
       __ veor(i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
     case kArmSimd128Not: {
       __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kArmSimd32x4Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
+    case kArmSimd128Select: {
+      // vbsl clobbers the mask input so make sure it was DefineSameAsFirst.
+      DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
       __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
               i.InputSimd128Register(2));
       break;
-    }
-    case kArmSimd16x8Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
-    }
-    case kArmSimd8x16Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
     }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb);
       break;
     case kCheckedLoadUint8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(ldrb);
       break;
     case kCheckedLoadInt16:
       ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsh);
       break;
@@ skipping 651 matching lines @@
       padding_size -= v8::internal::Assembler::kInstrSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8