[V8] Implement SIMD Boolean vector types to allow mask registers.

src/compiler/load-elimination.cc

Index: src/compiler/load-elimination.cc
diff --git a/src/compiler/load-elimination.cc b/src/compiler/load-elimination.cc
index 6c2935f7ca8d4a4867f336dfff59050d5d0770e9..2d6fead4282eb76bbd8f42f74491a179adddbb47 100644
--- a/src/compiler/load-elimination.cc
+++ b/src/compiler/load-elimination.cc
@@ -835,6 +835,9 @@ Reduction LoadElimination::ReduceStoreElement(Node* node) {
   // Only record the new value if the store doesn't have an implicit truncation.
   switch (access.machine_type.representation()) {
     case MachineRepresentation::kNone:
+    case MachineRepresentation::kSimdBool4:
+    case MachineRepresentation::kSimdBool8:
+    case MachineRepresentation::kSimdBool16:
     case MachineRepresentation::kBit:
       UNREACHABLE();
       break;
@@ -1037,6 +1040,9 @@ int LoadElimination::FieldIndexOf(FieldAccess const& access) {
     case MachineRepresentation::kNone:
     case MachineRepresentation::kBit:
     case MachineRepresentation::kSimd128:
+    case MachineRepresentation::kSimdBool4:
+    case MachineRepresentation::kSimdBool8:
+    case MachineRepresentation::kSimdBool16:
       UNREACHABLE();
       break;
     case MachineRepresentation::kWord32: