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Unified Diff: src/compiler/arm/code-generator-arm.cc

Issue 2700813002: [V8] Implement SIMD Boolean vector types to allow mask registers. (Closed)
Patch Set: Remove stray DCHECK. Created 3 years, 10 months ago
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Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index ca0174569dd662bd3af7853357b2401b5e8f593f..a0e85d63d54ce4733d380c5ada92a23857cd84b4 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -1927,25 +1927,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmSimd32x4Select: {
- // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
- __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
- i.InputSimd128Register(0));
+ // vbsl is a ternary opcode, so move input 0 into dest.
+ __ Move(i.OutputSimd128Register(), i.InputSimd128Register(0));
gdeepti 2017/02/17 17:51:48 Would it be possible to use DefineSameAsFirst in t
bbudge 2017/02/17 23:39:56 Yes, that seems better. Also, I noticed that these
__ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(2));
break;
}
case kArmSimd16x8Select: {
- // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
- __ vtst(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
- i.InputSimd128Register(0));
+ // vbsl is a ternary opcode, so move input 0 into dest.
+ __ Move(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(2));
break;
}
case kArmSimd8x16Select: {
- // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
- __ vtst(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
- i.InputSimd128Register(0));
+ // vbsl is a ternary opcode, so move input 0 into dest.
+ __ Move(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(2));
break;

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