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Side by Side Diff: src/compiler/opcodes.h

Issue 2700813002: [V8] Implement SIMD Boolean vector types to allow mask registers. (Closed)
Patch Set: Rebase. Created 3 years, 10 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_OPCODES_H_ 5 #ifndef V8_COMPILER_OPCODES_H_
6 #define V8_COMPILER_OPCODES_H_ 6 #define V8_COMPILER_OPCODES_H_
7 7
8 #include <iosfwd> 8 #include <iosfwd>
9 9
10 #include "src/globals.h" 10 #include "src/globals.h"
(...skipping 583 matching lines...) Expand 10 before | Expand all | Expand 10 after
594 V(Int32x4FromFloat32x4) \ 594 V(Int32x4FromFloat32x4) \
595 V(Uint32x4Min) \ 595 V(Uint32x4Min) \
596 V(Uint32x4Max) \ 596 V(Uint32x4Max) \
597 V(Uint32x4ShiftLeftByScalar) \ 597 V(Uint32x4ShiftLeftByScalar) \
598 V(Uint32x4ShiftRightByScalar) \ 598 V(Uint32x4ShiftRightByScalar) \
599 V(Uint32x4LessThan) \ 599 V(Uint32x4LessThan) \
600 V(Uint32x4LessThanOrEqual) \ 600 V(Uint32x4LessThanOrEqual) \
601 V(Uint32x4GreaterThan) \ 601 V(Uint32x4GreaterThan) \
602 V(Uint32x4GreaterThanOrEqual) \ 602 V(Uint32x4GreaterThanOrEqual) \
603 V(Uint32x4FromFloat32x4) \ 603 V(Uint32x4FromFloat32x4) \
604 V(CreateBool32x4) \
605 V(Bool32x4ReplaceLane) \
606 V(Bool32x4And) \ 604 V(Bool32x4And) \
607 V(Bool32x4Or) \ 605 V(Bool32x4Or) \
608 V(Bool32x4Xor) \ 606 V(Bool32x4Xor) \
609 V(Bool32x4Not) \ 607 V(Bool32x4Not) \
610 V(Bool32x4Swizzle) \
611 V(Bool32x4Shuffle) \
612 V(Bool32x4Equal) \
613 V(Bool32x4NotEqual) \
614 V(CreateInt16x8) \ 608 V(CreateInt16x8) \
615 V(Int16x8ReplaceLane) \ 609 V(Int16x8ReplaceLane) \
616 V(Int16x8Neg) \ 610 V(Int16x8Neg) \
617 V(Int16x8Add) \ 611 V(Int16x8Add) \
618 V(Int16x8AddSaturate) \ 612 V(Int16x8AddSaturate) \
619 V(Int16x8Sub) \ 613 V(Int16x8Sub) \
620 V(Int16x8SubSaturate) \ 614 V(Int16x8SubSaturate) \
621 V(Int16x8Mul) \ 615 V(Int16x8Mul) \
622 V(Int16x8Min) \ 616 V(Int16x8Min) \
623 V(Int16x8Max) \ 617 V(Int16x8Max) \
624 V(Int16x8ShiftLeftByScalar) \ 618 V(Int16x8ShiftLeftByScalar) \
625 V(Int16x8ShiftRightByScalar) \ 619 V(Int16x8ShiftRightByScalar) \
626 V(Int16x8Equal) \ 620 V(Int16x8Equal) \
627 V(Int16x8NotEqual) \ 621 V(Int16x8NotEqual) \
628 V(Int16x8LessThan) \ 622 V(Int16x8LessThan) \
629 V(Int16x8LessThanOrEqual) \ 623 V(Int16x8LessThanOrEqual) \
630 V(Int16x8GreaterThan) \ 624 V(Int16x8GreaterThan) \
631 V(Int16x8GreaterThanOrEqual) \ 625 V(Int16x8GreaterThanOrEqual) \
632 V(Uint16x8AddSaturate) \ 626 V(Uint16x8AddSaturate) \
633 V(Uint16x8SubSaturate) \ 627 V(Uint16x8SubSaturate) \
634 V(Uint16x8Min) \ 628 V(Uint16x8Min) \
635 V(Uint16x8Max) \ 629 V(Uint16x8Max) \
636 V(Uint16x8ShiftLeftByScalar) \ 630 V(Uint16x8ShiftLeftByScalar) \
637 V(Uint16x8ShiftRightByScalar) \ 631 V(Uint16x8ShiftRightByScalar) \
638 V(Uint16x8LessThan) \ 632 V(Uint16x8LessThan) \
639 V(Uint16x8LessThanOrEqual) \ 633 V(Uint16x8LessThanOrEqual) \
640 V(Uint16x8GreaterThan) \ 634 V(Uint16x8GreaterThan) \
641 V(Uint16x8GreaterThanOrEqual) \ 635 V(Uint16x8GreaterThanOrEqual) \
642 V(CreateBool16x8) \
643 V(Bool16x8ReplaceLane) \
644 V(Bool16x8And) \ 636 V(Bool16x8And) \
645 V(Bool16x8Or) \ 637 V(Bool16x8Or) \
646 V(Bool16x8Xor) \ 638 V(Bool16x8Xor) \
647 V(Bool16x8Not) \ 639 V(Bool16x8Not) \
648 V(Bool16x8Swizzle) \
649 V(Bool16x8Shuffle) \
650 V(Bool16x8Equal) \
651 V(Bool16x8NotEqual) \
652 V(CreateInt8x16) \ 640 V(CreateInt8x16) \
653 V(Int8x16ReplaceLane) \ 641 V(Int8x16ReplaceLane) \
654 V(Int8x16Neg) \ 642 V(Int8x16Neg) \
655 V(Int8x16Add) \ 643 V(Int8x16Add) \
656 V(Int8x16AddSaturate) \ 644 V(Int8x16AddSaturate) \
657 V(Int8x16Sub) \ 645 V(Int8x16Sub) \
658 V(Int8x16SubSaturate) \ 646 V(Int8x16SubSaturate) \
659 V(Int8x16Mul) \ 647 V(Int8x16Mul) \
660 V(Int8x16Min) \ 648 V(Int8x16Min) \
661 V(Int8x16Max) \ 649 V(Int8x16Max) \
662 V(Int8x16ShiftLeftByScalar) \ 650 V(Int8x16ShiftLeftByScalar) \
663 V(Int8x16ShiftRightByScalar) \ 651 V(Int8x16ShiftRightByScalar) \
664 V(Int8x16Equal) \ 652 V(Int8x16Equal) \
665 V(Int8x16NotEqual) \ 653 V(Int8x16NotEqual) \
666 V(Int8x16LessThan) \ 654 V(Int8x16LessThan) \
667 V(Int8x16LessThanOrEqual) \ 655 V(Int8x16LessThanOrEqual) \
668 V(Int8x16GreaterThan) \ 656 V(Int8x16GreaterThan) \
669 V(Int8x16GreaterThanOrEqual) \ 657 V(Int8x16GreaterThanOrEqual) \
670 V(Uint8x16AddSaturate) \ 658 V(Uint8x16AddSaturate) \
671 V(Uint8x16SubSaturate) \ 659 V(Uint8x16SubSaturate) \
672 V(Uint8x16Min) \ 660 V(Uint8x16Min) \
673 V(Uint8x16Max) \ 661 V(Uint8x16Max) \
674 V(Uint8x16ShiftLeftByScalar) \ 662 V(Uint8x16ShiftLeftByScalar) \
675 V(Uint8x16ShiftRightByScalar) \ 663 V(Uint8x16ShiftRightByScalar) \
676 V(Uint8x16LessThan) \ 664 V(Uint8x16LessThan) \
677 V(Uint8x16LessThanOrEqual) \ 665 V(Uint8x16LessThanOrEqual) \
678 V(Uint8x16GreaterThan) \ 666 V(Uint8x16GreaterThan) \
679 V(Uint8x16GreaterThanOrEqual) \ 667 V(Uint8x16GreaterThanOrEqual) \
680 V(CreateBool8x16) \
681 V(Bool8x16ReplaceLane) \
682 V(Bool8x16And) \ 668 V(Bool8x16And) \
683 V(Bool8x16Or) \ 669 V(Bool8x16Or) \
684 V(Bool8x16Xor) \ 670 V(Bool8x16Xor) \
685 V(Bool8x16Not) \ 671 V(Bool8x16Not) \
686 V(Bool8x16Swizzle) \
687 V(Bool8x16Shuffle) \
688 V(Bool8x16Equal) \
689 V(Bool8x16NotEqual) \
690 V(Simd128And) \ 672 V(Simd128And) \
691 V(Simd128Or) \ 673 V(Simd128Or) \
692 V(Simd128Xor) \ 674 V(Simd128Xor) \
693 V(Simd128Not) \ 675 V(Simd128Not) \
694 V(Simd32x4Select) \ 676 V(Simd32x4Select) \
695 V(Simd32x4Swizzle) \ 677 V(Simd32x4Swizzle) \
696 V(Simd32x4Shuffle) \ 678 V(Simd32x4Shuffle) \
697 V(Simd16x8Select) \ 679 V(Simd16x8Select) \
698 V(Simd16x8Swizzle) \ 680 V(Simd16x8Swizzle) \
699 V(Simd16x8Shuffle) \ 681 V(Simd16x8Shuffle) \
700 V(Simd8x16Select) \ 682 V(Simd8x16Select) \
701 V(Simd8x16Swizzle) \ 683 V(Simd8x16Swizzle) \
702 V(Simd8x16Shuffle) 684 V(Simd8x16Shuffle)
703 685
704 #define MACHINE_SIMD_RETURN_NUM_OP_LIST(V) \ 686 #define MACHINE_SIMD_RETURN_NUM_OP_LIST(V) \
705 V(Float32x4ExtractLane) \ 687 V(Float32x4ExtractLane) \
706 V(Int32x4ExtractLane) \ 688 V(Int32x4ExtractLane) \
707 V(Int16x8ExtractLane) \ 689 V(Int16x8ExtractLane) \
708 V(Int8x16ExtractLane) 690 V(Int8x16ExtractLane)
709 691
710 #define MACHINE_SIMD_RETURN_BOOL_OP_LIST(V) \ 692 #define MACHINE_SIMD_RETURN_BOOL_OP_LIST(V) \
711 V(Bool32x4ExtractLane) \
712 V(Bool32x4AnyTrue) \ 693 V(Bool32x4AnyTrue) \
713 V(Bool32x4AllTrue) \ 694 V(Bool32x4AllTrue) \
714 V(Bool16x8ExtractLane) \
715 V(Bool16x8AnyTrue) \ 695 V(Bool16x8AnyTrue) \
716 V(Bool16x8AllTrue) \ 696 V(Bool16x8AllTrue) \
717 V(Bool8x16ExtractLane) \
718 V(Bool8x16AnyTrue) \ 697 V(Bool8x16AnyTrue) \
719 V(Bool8x16AllTrue) 698 V(Bool8x16AllTrue)
720 699
721 #define MACHINE_SIMD_GENERIC_OP_LIST(V) \ 700 #define MACHINE_SIMD_GENERIC_OP_LIST(V) \
722 V(Simd128Load) \ 701 V(Simd128Load) \
723 V(Simd128Load1) \ 702 V(Simd128Load1) \
724 V(Simd128Load2) \ 703 V(Simd128Load2) \
725 V(Simd128Load3) \ 704 V(Simd128Load3) \
726 V(Simd128Store) \ 705 V(Simd128Store) \
727 V(Simd128Store1) \ 706 V(Simd128Store1) \
(...skipping 88 matching lines...) Expand 10 before | Expand all | Expand 10 after
816 } 795 }
817 }; 796 };
818 797
819 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream&, IrOpcode::Value); 798 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream&, IrOpcode::Value);
820 799
821 } // namespace compiler 800 } // namespace compiler
822 } // namespace internal 801 } // namespace internal
823 } // namespace v8 802 } // namespace v8
824 803
825 #endif // V8_COMPILER_OPCODES_H_ 804 #endif // V8_COMPILER_OPCODES_H_
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