Add several SIMD opcodes to IA32

src/compiler/ia32/code-generator-ia32.cc

Index: src/compiler/ia32/code-generator-ia32.cc
diff --git a/src/compiler/ia32/code-generator-ia32.cc b/src/compiler/ia32/code-generator-ia32.cc
index f94f6bc21184630ecee0b5bb1d47fc7bd6f9b7db..787f3ad23e5e15d0d85e87dfbff0282b301b2bd9 100644
--- a/src/compiler/ia32/code-generator-ia32.cc
+++ b/src/compiler/ia32/code-generator-ia32.cc
@@ -1906,6 +1906,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ xchg(i.InputRegister(index), operand);
       break;
     }
+    case kIA32Int32x4Create: {
+      XMMRegister dst = i.OutputSimd128Register();
+      __ movd(dst, i.InputOperand(0));
+      __ pshufd(dst, dst, 0x0);
+      break;
+    }
+    case kIA32Int32x4ExtractLane: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);

[bbudge, 2017/02/22 21:51:10]

This scope is taken by the macro assembler function.

[Jing, 2017/02/23 07:28:17]

Done.
I adjusted Pextrd macro to support non-SSE4 occasion.

+      __ Pextrd(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
+      break;
+    }
+    case kIA32Int32x4ReplaceLane: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);

[bbudge, 2017/02/22 21:51:10]

Ditto

[Jing, 2017/02/23 07:28:16]

I cannot remove the SSE4 check here, because it will cause error on non-SSE4
hardware. To avoid redundant scope, I change Pinsrd macro to raw pinsrd.

When SSE4 is not supported, Pinsrd will use some SSE2 instructions to handle
specific cases for kSSEFloat64InsertLowWord32 and kSSEFloat64InsertHighWord32.
But the specific path is wrong for the semantic meaning of "pinsrd", because it
doesn't care about the high 64 bits of xmm register.

I haven't find a proper way to emulate non-SSE4 Pinsrd similar to Pextrd,and I'm
still seeking. Do you have any suggestions?

[bbudge, 2017/02/24 18:28:54]

I don't have any suggestions. I've found googling effective to find the best
SIMD code sequences for various operations. I'm worried about performance issues
from mixing the various instructions together. I think we've had problems mixing
SSE and AVX.

+      __ Pinsrd(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
+      break;
+    }
+    case kSSEInt32x4Add: {

[bbudge, 2017/02/22 21:51:10]

SSE scope?

[Jing, 2017/02/23 07:28:16]

paddd and psubd are both SSE2 instructions. I guess that they are assumed on by
default and need no scope?

[bbudge, 2017/02/24 18:28:54]

OK

+      __ paddd(i.OutputSimd128Register(), i.InputOperand(1));
+      break;
+    }
+    case kSSEInt32x4Sub: {

[bbudge, 2017/02/22 21:51:10]

Ditto

+      __ psubd(i.OutputSimd128Register(), i.InputOperand(1));
+      break;
+    }
+    case kAVXInt32x4Add: {
+      CpuFeatureScope avx_scope(masm(), AVX);
+      __ vpaddd(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputOperand(1));
+      break;
+    }
+    case kAVXInt32x4Sub: {
+      CpuFeatureScope avx_scope(masm(), AVX);
+      __ vpsubd(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputOperand(1));
+      break;
+    }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movsx_b);
       break;