Add several SIMD opcodes to IA32

src/ia32/macro-assembler-ia32.cc

Index: src/ia32/macro-assembler-ia32.cc
diff --git a/src/ia32/macro-assembler-ia32.cc b/src/ia32/macro-assembler-ia32.cc
index 906c369172086454690cf6b6d612ff8204d3bc8a..e8842a83238bda9242981aeb8cc42fb2197dae56 100644
--- a/src/ia32/macro-assembler-ia32.cc
+++ b/src/ia32/macro-assembler-ia32.cc
@@ -2270,32 +2270,41 @@ void MacroAssembler::Pextrd(Register dst, XMMRegister src, int8_t imm8) {
     movd(dst, src);
     return;
   }
-  DCHECK_EQ(1, imm8);
   if (CpuFeatures::IsSupported(SSE4_1)) {
     CpuFeatureScope sse_scope(this, SSE4_1);
     pextrd(dst, src, imm8);
     return;
   }
-  pshufd(xmm0, src, 1);
+  DCHECK_LT(imm8, 4);
+  pshufd(xmm0, src, imm8);
   movd(dst, xmm0);
 }
 
-
-void MacroAssembler::Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8) {
-  DCHECK(imm8 == 0 || imm8 == 1);
+void MacroAssembler::Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8,
+                            bool is_64_bits) {
   if (CpuFeatures::IsSupported(SSE4_1)) {
     CpuFeatureScope sse_scope(this, SSE4_1);
     pinsrd(dst, src, imm8);
     return;
   }
-  movd(xmm0, src);
-  if (imm8 == 1) {
-    punpckldq(dst, xmm0);
+  if (is_64_bits) {
+    movd(xmm0, src);
+    if (imm8 == 1) {
+      punpckldq(dst, xmm0);
+    } else {
+      DCHECK_EQ(0, imm8);
+      psrlq(dst, 32);
+      punpckldq(xmm0, dst);
+      movaps(dst, xmm0);
+    }
   } else {
-    DCHECK_EQ(0, imm8);
-    psrlq(dst, 32);
-    punpckldq(xmm0, dst);
-    movaps(dst, xmm0);
+    DCHECK_LT(imm8, 4);
+    push(eax);
+    mov(eax, src);
+    pinsrw(dst, eax, imm8 * 2);
+    shr(eax, 16);
+    pinsrw(dst, eax, imm8 * 2 + 1);
+    pop(eax);
   }
 }