Add several SIMD opcodes to IA32

src/compiler/ia32/instruction-selector-ia32.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
 namespace v8 {
@@ skipping 1673 matching lines @@
     addressing_mode = kMode_MRI;
   } else {
     inputs[input_count++] = g.UseUniqueRegister(index);
     addressing_mode = kMode_MR1;
   }
   inputs[input_count++] = g.UseUniqueRegister(value);
   InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
   Emit(code, 0, nullptr, input_count, inputs);
 }
 
+void InstructionSelector::VisitCreateInt32x4(Node* node) {
+  IA32OperandGenerator g(this);
+  Emit(kIA32Int32x4Create, g.DefineAsRegister(node), g.Use(node->InputAt(0)));

[bbudge, 2017/02/18 00:02:25]

Call VisitRO(this, node, kIA32Int32x4Create)

[Jing, 2017/02/20 15:28:13]

Done.

+}
+
+void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
+  IA32OperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kIA32Int32x4ExtractLane, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
+}
+
+void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) {
+  IA32OperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kIA32Int32x4ReplaceLane, g.DefineSameAsFirst(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
+       g.Use(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt32x4Add(Node* node) {
+  IA32OperandGenerator g(this);
+  Emit(kIA32Int32x4Add, g.DefineSameAsFirst(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));

[bbudge, 2017/02/18 00:02:25]

If there will be a lot of similar methods here, it would be good to factor out
the common code into a new VisitRRR function at the top of this file, and call
that in this method and the one below.

[Jing, 2017/02/20 15:28:13]

Actually I found that g.UseRegister(node->InputAt(1)) is too narrow here. We can
write g.Use(). Sorry for my thoughtless porting from x64 ...

Int32x4Add can be implemented by "PADDD xmm1, xmm2/m128" or "VPADDD xmm1, xmm2,
xmm3/m128", and they match VisitRROFloat
(https://chromium.googlesource.com/v8/v8.git/+/master/src/compiler/ia32/instru...).
So I guess the best way is to put it in RRO_FLOAT_OP_LIST, and add the AVX
version in this patch?

I did similar change on Int32x4Sub. AVX version of other SIMD opcodes will be
added in later patches.

[bbudge, 2017/02/22 21:51:10]

Thanks!

+}
+
+void InstructionSelector::VisitInt32x4Sub(Node* node) {
+  IA32OperandGenerator g(this);
+  Emit(kIA32Int32x4Sub, g.DefineSameAsFirst(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags =
       MachineOperatorBuilder::kWord32ShiftIsSafe |
       MachineOperatorBuilder::kWord32Ctz;
   if (CpuFeatures::IsSupported(POPCNT)) {
     flags |= MachineOperatorBuilder::kWord32Popcnt;
   }
   if (CpuFeatures::IsSupported(SSE4_1)) {
@@ skipping 12 matching lines @@
 // static
 MachineOperatorBuilder::AlignmentRequirements
 InstructionSelector::AlignmentRequirements() {
   return MachineOperatorBuilder::AlignmentRequirements::
       FullUnalignedAccessSupport();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8