Only assume that we have 32 D registers on ARMv7-a.

runtime/vm/constants_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM_H_
 #define VM_CONSTANTS_ARM_H_
 
+#include "platform/globals.h"
 #include "platform/assert.h"
 
 namespace dart {
 
 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at
 // a time.
-// TODO(zra): Detect number of registers at runtime by querying /proc/cpuinfo.
+#if defined(__ARM_ARCH_7A__)
 #define VFPv3_D32
+#elif defined(TARGET_ARCH_ARM) && !defined(HOST_ARCH_ARM)
+// If we're running in the simulator, use all 32.
+#define VFPv3_D32
+#else
+#define VFPv3_D16
+#endif
 #if defined(VFPv3_D16) == defined(VFPv3_D32)
 #error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time."
 #endif
 
 
 enum Register {
+  kNoRegister = -1,
   kFirstFreeCpuRegister = 0,
   R0  =  0,
   R1  =  1,
   R2  =  2,
   R3  =  3,
   R4  =  4,
   R5  =  5,
   R6  =  6,
   R7  =  7,
   R8  =  8,
   kLastFreeCpuRegister = 8,
   R9  =  9,
   R10 = 10,
   R11 = 11,
   R12 = 12,
   R13 = 13,
   R14 = 14,
   R15 = 15,
   FP  = 11,
   IP  = 12,
   SP  = 13,
   LR  = 14,
   PC  = 15,
   kNumberOfCpuRegisters = 16,
-  kNoRegister = -1,
 };
 
 
 // Values for single-precision floating point registers.
 enum SRegister {
+  kNoSRegister = -1,
   S0  =  0,
   S1  =  1,
   S2  =  2,
   S3  =  3,
   S4  =  4,
   S5  =  5,
   S6  =  6,
   S7  =  7,
   S8  =  8,
   S9  =  9,
@@ skipping 13 matching lines @@
   S23 = 23,
   S24 = 24,
   S25 = 25,
   S26 = 26,
   S27 = 27,
   S28 = 28,
   S29 = 29,
   S30 = 30,
   S31 = 31,
   kNumberOfSRegisters = 32,
-  kNoSRegister = -1,
 };
 
 
 // Values for double-precision floating point registers.
 enum DRegister {
+  kNoDRegister = -1,
   D0  =  0,
   D1  =  1,
   D2  =  2,
   D3  =  3,
   D4  =  4,
   D5  =  5,
   D6  =  6,
   D7  =  7,
   D8  =  8,
   D9  =  9,
   D10 = 10,
   D11 = 11,
   D12 = 12,
   D13 = 13,
   D14 = 14,
   D15 = 15,
 #ifdef VFPv3_D16
   kNumberOfDRegisters = 16,
+  // Leaving these defined, but marking them as kNoDRegister to avoid polluting
+  // other parts of the code with #ifdef's. Instead, query kNumberOfDRegisters
+  // to see which registers are valid.
+  D16 = kNoDRegister,
+  D17 = kNoDRegister,
+  D18 = kNoDRegister,
+  D19 = kNoDRegister,
+  D20 = kNoDRegister,
+  D21 = kNoDRegister,
+  D22 = kNoDRegister,
+  D23 = kNoDRegister,
+  D24 = kNoDRegister,
+  D25 = kNoDRegister,
+  D26 = kNoDRegister,
+  D27 = kNoDRegister,
+  D28 = kNoDRegister,
+  D29 = kNoDRegister,
+  D30 = kNoDRegister,
+  D31 = kNoDRegister,
 #else
   D16 = 16,
   D17 = 17,
   D18 = 18,
   D19 = 19,
   D20 = 20,
   D21 = 21,
   D22 = 22,
   D23 = 23,
   D24 = 24,
   D25 = 25,
   D26 = 26,
   D27 = 27,
   D28 = 28,
   D29 = 29,
   D30 = 30,
   D31 = 31,
   kNumberOfDRegisters = 32,
 #endif
   kNumberOfOverlappingDRegisters = 16,
-  kNoDRegister = -1,
 };
 
 
 enum QRegister {
+  kNoQRegister = -1,
   Q0  =  0,
   Q1  =  1,
   Q2  =  2,
   Q3  =  3,
   Q4  =  4,
   Q5  =  5,
   Q6  =  6,
   Q7  =  7,
 #ifdef VFPv3_D16
   kNumberOfQRegisters = 8,
+  Q8  = kNoQRegister,
+  Q9  = kNoQRegister,
+  Q10 = kNoQRegister,
+  Q11 = kNoQRegister,
+  Q12 = kNoQRegister,
+  Q13 = kNoQRegister,
+  Q14 = kNoQRegister,
+  Q15 = kNoQRegister,
 #else
   Q8  =  8,
   Q9  =  9,
   Q10 = 10,
   Q11 = 11,
   Q12 = 12,
   Q13 = 13,
   Q14 = 14,
   Q15 = 15,
   kNumberOfQRegisters = 16,
 #endif
-  kNoQRegister = -1,
 };
 
 
 static inline DRegister EvenDRegisterOf(QRegister q) {
   return static_cast<DRegister>(q * 2);
 }
 
 static inline DRegister OddDRegisterOf(QRegister q) {
   return static_cast<DRegister>((q * 2) + 1);
 }
 
 
 static inline SRegister EvenSRegisterOf(DRegister d) {
-#ifdef VFPv3_D32
+#if defined(VFPv3_D32)
+  // When we have 32 D registers, the S registers only overlap the first 16.
+  // That is, there are only 32 S registers.
   ASSERT(d < D16);
 #endif
   return static_cast<SRegister>(d * 2);
 }
 
 static inline SRegister OddSRegisterOf(DRegister d) {
-#ifdef VFPv3_D32
+#if defined(VFPv3_D32)
   ASSERT(d < D16);
 #endif
   return static_cast<SRegister>((d * 2) + 1);
 }
 
 
 // Register aliases for floating point scratch registers.
 const QRegister QTMP = Q7;  // Overlaps with DTMP, STMP.
 const DRegister DTMP = EvenDRegisterOf(QTMP);  // Overlaps with STMP.
 const SRegister STMP = EvenSRegisterOf(DTMP);
@@ skipping 472 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM_H_