Adds single-precision and SIMD load/store to arm64.

runtime/vm/assembler_arm64_test.cc

Index: runtime/vm/assembler_arm64_test.cc
===================================================================
--- runtime/vm/assembler_arm64_test.cc	(revision 35908)
+++ runtime/vm/assembler_arm64_test.cc	(working copy)
@@ -1551,6 +1551,45 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(FldrsFstrsPrePostIndex, assembler) {
+  __ LoadDImmediate(V1, 42.0, kNoPP);
+  __ fcvtsd(V2, V1);
+  __ fstrs(V2, Address(SP, -1*kWordSize, Address::PreIndex));
+  __ fldrs(V3, Address(SP, 1*kWordSize, Address::PostIndex));
+  __ fcvtds(V0, V3);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FldrsFstrsPrePostIndex, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(FldrqFstrqPrePostIndex, assembler) {
+  __ LoadDImmediate(V1, 21.0, kNoPP);
+  __ LoadDImmediate(V2, 21.0, kNoPP);
+  __ LoadImmediate(R1, 42, kNoPP);
+  __ Push(R1);
+  __ PushDouble(V1);
+  __ PushDouble(V2);
+  __ fldrq(V3, Address(SP, 2 * kWordSize, Address::PostIndex));
+  __ Pop(R0);
+  __ fstrq(V3, Address(SP, -2 * kWordSize, Address::PreIndex));
+  __ PopDouble(V0);
+  __ PopDouble(V1);
+  __ faddd(V0, V0, V1);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FldrqFstrqPrePostIndex, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
 ASSEMBLER_TEST_GENERATE(Fcvtzds, assembler) {
   __ LoadDImmediate(V0, 42.0, kNoPP);
   __ fcvtzds(R0, V0);