Adds single-precision and SIMD load/store to arm64.

runtime/vm/simulator_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
@@ skipping 598 matching lines @@
 int32_t Simulator::get_wregister(Register reg, R31Type r31t) const {
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   if ((reg == R31) && (r31t == R31IsZR)) {
     return 0;
   } else {
     return registers_[reg];
   }
 }
 
 
-int64_t Simulator::get_vregisterd(VRegister reg) {
+int64_t Simulator::get_vregisterd(VRegister reg) const {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   return vregisters_[reg].lo;
 }
 
 
 void Simulator::set_vregisterd(VRegister reg, int64_t value) {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   vregisters_[reg].lo = value;
   vregisters_[reg].hi = 0;
 }
 
 
+void Simulator::get_vregister(VRegister reg, simd_value_t* value) const {
+  ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
+  value->lo = vregisters_[reg].lo;
+  value->hi = vregisters_[reg].hi;
+}
+
+
+void Simulator::set_vregister(VRegister reg, const simd_value_t& value) {
+  ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
+  vregisters_[reg].lo = value.lo;
+  vregisters_[reg].hi = value.hi;
+}
+
+
 // Raw access to the PC register.
 void Simulator::set_pc(int64_t value) {
   pc_modified_ = true;
   last_pc_ = pc_;
   pc_ = value;
 }
 
 
 // Raw access to the pc.
 int64_t Simulator::get_pc() const {
@@ skipping 760 matching lines @@
   }
 }
 
 
 void Simulator::DecodeLoadStoreReg(Instr* instr) {
   // Calculate the address.
   const Register rn = instr->RnField();
   const Register rt = instr->RtField();
   const VRegister vt = instr->VtField();
   const int64_t rn_val = get_register(rn, R31IsSP);
-  const uint32_t size = instr->SzField();
+  const uint32_t size =
+      (instr->Bit(26) == 1) ? ((instr->Bit(23) << 2) | instr->SzField())
+                            : instr->SzField();
   uword address = 0;
   uword wb_address = 0;
   bool wb = false;
   if (instr->Bit(24) == 1) {
     // addr = rn + scaled unsigned 12-bit immediate offset.
     const uint32_t imm12 = static_cast<uint32_t>(instr->Imm12Field());
     const uint32_t offset = imm12 << size;
     address = rn_val + offset;
   }  else if (instr->Bits(10, 2) == 0) {
     // addr = rn + signed 9-bit immediate offset.
@@ skipping 28 matching lines @@
     return;
   }
 
   // Check the address.
   if (IsIllegalAddress(address)) {
     HandleIllegalAccess(address, instr);
     return;
   }
 
   // Do access.
-  if (instr->Bits(22, 2) == 0) {
-    if (instr->Bit(26) == 1) {
-      // Format(instr, "vstrd 'vt, 'memop");
-      if (size != 3) {
-        UnimplementedInstruction(instr);
-        return;
+  if (instr->Bit(26) == 1) {
+    if (instr->Bit(22) == 0) {
+      // Format(instr, "fstr'fsz 'vt, 'memop");
+      const int64_t vt_val = get_vregisterd(vt);
+      switch (size) {
+        case 2:
+          WriteW(address, vt_val & kWRegMask, instr);
+          break;
+        case 3:
+          WriteX(address, vt_val, instr);
+          break;
+        case 4: {
+          simd_value_t val;
+          get_vregister(vt, &val);
+          WriteX(address, val.lo, instr);
+          WriteX(address + kWordSize, val.hi, instr);
+          break;
+        }
+        default:
+          UnimplementedInstruction(instr);
+          return;
       }
-      const int64_t vt_val = get_vregisterd(vt);
-      WriteX(address, vt_val, instr);
     } else {
+      // Format(instr, "fldr'fsz 'vt, 'memop");
+      switch (size) {
+        case 2:
+          set_vregisterd(vt, static_cast<int64_t>(ReadWU(address, instr)));
+          break;
+        case 3:
+          set_vregisterd(vt, ReadX(address, instr));
+          break;
+        case 4: {
+          simd_value_t val;
+          val.lo = ReadX(address, instr);
+          val.hi = ReadX(address + kWordSize, instr);
+          set_vregister(vt, val);
+          break;
+        }
+        default:
+          UnimplementedInstruction(instr);
+          return;
+      }
+    }
+  } else {
+    if (instr->Bits(22, 2) == 0) {
       // Format(instr, "str'sz 'rt, 'memop");
       const int32_t rt_val32 = get_wregister(rt, R31IsZR);
       switch (size) {
         case 0: {
           const uint8_t val = static_cast<uint8_t>(rt_val32);
           WriteB(address, val);
           break;
         }
         case 1: {
           const uint16_t val = static_cast<uint16_t>(rt_val32);
           WriteH(address, val, instr);
           break;
         }
         case 2: {
           const uint32_t val = static_cast<uint32_t>(rt_val32);
           WriteW(address, val, instr);
           break;
         }
         case 3: {
           const int64_t val = get_register(rt, R31IsZR);
           WriteX(address, val, instr);
           break;
         }
         default:
           UNREACHABLE();
           break;
       }
-    }
-  } else {
-    if (instr->Bit(26) == 1) {
-      // Format(instr, "ldrd 'vt, 'memop");
-      if ((size != 3) || (instr->Bit(23) != 0)) {
-        UnimplementedInstruction(instr);
-        return;
-      }
-      const int64_t val = ReadX(address, instr);
-      set_vregisterd(vt, val);
     } else {
       // Format(instr, "ldr'sz 'rt, 'memop");
       // Undefined case.
       if ((size == 3) && (instr->Bits(22, 2) == 3)) {
         UnimplementedInstruction(instr);
         return;
       }
 
       // Read the value.
       const bool signd = instr->Bit(23) == 1;
@@ skipping 560 matching lines @@
     // Format(instr, "fcvtzds 'rd, 'vn");
     const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn));
     set_register(rd, static_cast<int64_t>(vn_val), instr->RdMode());
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeFPOneSource(Instr* instr) {
-  const int opc = instr->Bits(15, 2);
+  const int opc = instr->Bits(15, 6);
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
   const int64_t vn_val = get_vregisterd(vn);
+  const int32_t vn_val32 = vn_val & kWRegMask;
   const double vn_dbl = bit_cast<double, int64_t>(vn_val);
+  const float vn_flt = bit_cast<float, int32_t>(vn_val32);
+
+  if ((opc != 5) && (instr->Bit(22) != 1)) {
+    // Source is interpreted as single-precision only if we're doing a
+    // conversion from single -> double.
+    UnimplementedInstruction(instr);
+    return;
+  }
 
   int64_t res_val = 0;
   switch (opc) {
     case 0:
       // Format("fmovdd 'vd, 'vn");
       res_val = get_vregisterd(vn);
       break;
     case 1:
       // Format("fabsd 'vd, 'vn");
       res_val = bit_cast<int64_t, double>(fabs(vn_dbl));
       break;
     case 2:
       // Format("fnegd 'vd, 'vn");
       res_val = bit_cast<int64_t, double>(-vn_dbl);
       break;
     case 3:
       // Format("fsqrtd 'vd, 'vn");
       res_val = bit_cast<int64_t, double>(sqrt(vn_dbl));
       break;
+    case 4: {
+      // Format(instr, "fcvtsd 'vd, 'vn");
+      const uint32_t val =
+          bit_cast<uint32_t, float>(static_cast<float>(vn_dbl));
+      res_val = static_cast<int64_t>(val);
+      break;
+    }
+    case 5:
+      // Format(instr, "fcvtds 'vd, 'vn");
+      res_val = bit_cast<int64_t, double>(static_cast<double>(vn_flt));
+      break;
     default:
-      UNREACHABLE();
+      UnimplementedInstruction(instr);
       break;
   }
 
   set_vregisterd(vd, res_val);
 }
 
 
 void Simulator::DecodeFPTwoSource(Instr* instr) {
   if (instr->Bits(22, 2) != 1) {
     UnimplementedInstruction(instr);
@@ skipping 287 matching lines @@
   set_register(kExceptionObjectReg, bit_cast<int64_t>(raw_exception));
   set_register(kStackTraceObjectReg, bit_cast<int64_t>(raw_stacktrace));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM64)
 
 #endif  // defined TARGET_ARCH_ARM64