Adds single-precision and SIMD load/store to arm64.

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 654 matching lines @@
     cmn(rn, op);
   } else {
     ASSERT(rn != TMP2);
     LoadImmediate(TMP2, imm, pp);
     cmp(rn, Operand(TMP2));
   }
 }
 
 
 void Assembler::LoadFromOffset(
-    Register dest, Register base, int32_t offset, OperandSize sz) {
+    Register dest, Register base, int32_t offset, Register pp, OperandSize sz) {
   if (Address::CanHoldOffset(offset, Address::Offset, sz)) {
     ldr(dest, Address(base, offset, Address::Offset, sz), sz);
   } else {
     ASSERT(base != TMP2);
-    // Since offset is 32-bits, it won't be loaded from the pool.
-    AddImmediate(TMP2, base, offset, kNoPP);
+    AddImmediate(TMP2, base, offset, pp);
     ldr(dest, Address(TMP2), sz);
   }
 }
 
 
-void Assembler::LoadDFromOffset(VRegister dest, Register base, int32_t offset) {
+void Assembler::LoadDFromOffset(
+    VRegister dest, Register base, int32_t offset, Register pp) {
   if (Address::CanHoldOffset(offset, Address::Offset, kDWord)) {
     fldrd(dest, Address(base, offset, Address::Offset, kDWord));
   } else {
     ASSERT(base != TMP2);
-    // Since offset is 32-bits, it won't be loaded from the pool.
-    AddImmediate(TMP2, base, offset, kNoPP);
+    AddImmediate(TMP2, base, offset, pp);
     fldrd(dest, Address(TMP2));
   }
 }
 
 
+void Assembler::LoadQFromOffset(
+    VRegister dest, Register base, int32_t offset, Register pp) {
+  if (Address::CanHoldOffset(offset, Address::Offset, kQWord)) {
+    fldrq(dest, Address(base, offset, Address::Offset, kQWord));
+  } else {
+    ASSERT(base != TMP2);
+    AddImmediate(TMP2, base, offset, pp);
+    fldrq(dest, Address(TMP2));
+  }
+}
+
+
 void Assembler::StoreToOffset(
-    Register src, Register base, int32_t offset, OperandSize sz) {
+    Register src, Register base, int32_t offset, Register pp, OperandSize sz) {
   ASSERT(base != TMP2);
   if (Address::CanHoldOffset(offset, Address::Offset, sz)) {
     str(src, Address(base, offset, Address::Offset, sz), sz);
   } else {
     ASSERT(src != TMP2);
-    // Since offset is 32-bits, it won't be loaded from the pool.
-    AddImmediate(TMP2, base, offset, kNoPP);
+    AddImmediate(TMP2, base, offset, pp);
     str(src, Address(TMP2), sz);
   }
 }
 
 
-void Assembler::StoreDToOffset(VRegister src, Register base, int32_t offset) {
+void Assembler::StoreDToOffset(
+    VRegister src, Register base, int32_t offset, Register pp) {
   if (Address::CanHoldOffset(offset, Address::Offset, kDWord)) {
     fstrd(src, Address(base, offset, Address::Offset, kDWord));
   } else {
     ASSERT(base != TMP2);
-    // Since offset is 32-bits, it won't be loaded from the pool.
-    AddImmediate(TMP2, base, offset, kNoPP);
+    AddImmediate(TMP2, base, offset, pp);
     fstrd(src, Address(TMP2));
   }
 }
 
 
+void Assembler::StoreQToOffset(
+    VRegister src, Register base, int32_t offset, Register pp) {
+  if (Address::CanHoldOffset(offset, Address::Offset, kQWord)) {
+    fstrq(src, Address(base, offset, Address::Offset, kQWord));
+  } else {
+    ASSERT(base != TMP2);
+    AddImmediate(TMP2, base, offset, pp);
+    fstrq(src, Address(TMP2));
+  }
+}
+
+
 // Store into object.
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0), young_alignment);
 
   // Write-barrier triggers if the value is in the new space (has bit set) and
   // the object is in the old space (has bit cleared).
@@ skipping 12 matching lines @@
   // For the value we are only interested in the new/old bit and the tag bit.
   // And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
   and_(TMP, value, Operand(value, LSL, kObjectAlignmentLog2 - 1));
   // And the result with the negated space bit of the object.
   bic(TMP, TMP, Operand(object));
   tsti(TMP, kNewObjectAlignmentOffset);
   b(no_update, EQ);
 }
 
 
+void Assembler::StoreIntoObjectOffset(Register object,
+                                      int32_t offset,
+                                      Register value,
+                                      Register pp,
+                                      bool can_value_be_smi) {
+  if (Address::CanHoldOffset(offset - kHeapObjectTag)) {
+    StoreIntoObject(
+        object, FieldAddress(object, offset), value, can_value_be_smi);
+  } else {
+    AddImmediate(TMP, object, offset - kHeapObjectTag, pp);
+    StoreIntoObject(object, Address(TMP), value, can_value_be_smi);
+  }
+}
+
+
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
   str(value, dest);
   Label done;
   if (can_value_be_smi) {
     StoreIntoObjectFilter(object, value, &done);
   } else {
@@ skipping 25 matching lines @@
 #if defined(DEBUG)
   Label done;
   StoreIntoObjectFilter(object, value, &done);
   Stop("Store buffer update is required");
   Bind(&done);
 #endif  // defined(DEBUG)
   // No store buffer update.
 }
 
 
+void Assembler::StoreIntoObjectOffsetNoBarrier(Register object,
+                                               int32_t offset,
+                                               Register value,
+                                               Register pp) {
+  if (Address::CanHoldOffset(offset - kHeapObjectTag)) {
+    StoreIntoObjectNoBarrier(object, FieldAddress(object, offset), value);
+  } else {
+    AddImmediate(TMP, object, offset - kHeapObjectTag, pp);
+    StoreIntoObjectNoBarrier(object, Address(TMP), value);
+  }
+}
+
+
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          const Object& value) {
   ASSERT(value.IsSmi() || value.InVMHeap() ||
          (value.IsOld() && value.IsNotTemporaryScopedHandle()));
   // No store buffer update.
-  LoadObject(TMP, value, PP);
-  str(TMP, dest);
+  LoadObject(TMP2, value, PP);
+  str(TMP2, dest);
 }
 
 
-void Assembler::LoadClassId(Register result, Register object) {
+void Assembler::StoreIntoObjectOffsetNoBarrier(Register object,
+                                               int32_t offset,
+                                               const Object& value,
+                                               Register pp) {
+  if (Address::CanHoldOffset(offset - kHeapObjectTag)) {
+    StoreIntoObjectNoBarrier(object, FieldAddress(object, offset), value);
+  } else {
+    AddImmediate(TMP, object, offset - kHeapObjectTag, pp);
+    StoreIntoObjectNoBarrier(object, Address(TMP), value);
+  }
+}
+
+
+void Assembler::LoadClassId(Register result, Register object, Register pp) {
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
   const intptr_t class_id_offset = Object::tags_offset() +
       RawObject::kClassIdTagPos / kBitsPerByte;
-  LoadFromOffset(result, object, class_id_offset - kHeapObjectTag,
+  LoadFromOffset(result, object, class_id_offset - kHeapObjectTag, pp,
                  kUnsignedHalfword);
 }
 
 
-void Assembler::LoadClassById(Register result, Register class_id) {
+void Assembler::LoadClassById(Register result, Register class_id, Register pp) {
   ASSERT(result != class_id);
-  LoadFieldFromOffset(result, CTX, Context::isolate_offset());
+  LoadFieldFromOffset(result, CTX, Context::isolate_offset(), pp);
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
-  LoadFromOffset(result, result, table_offset_in_isolate);
+  LoadFromOffset(result, result, table_offset_in_isolate, pp);
   ldr(result, Address(result, class_id, UXTX, Address::Scaled));
 }
 
 
-void Assembler::LoadClass(Register result, Register object) {
+void Assembler::LoadClass(Register result, Register object, Register pp) {
   ASSERT(object != TMP);
-  LoadClassId(TMP, object);
-  LoadClassById(result, TMP);
+  LoadClassId(TMP, object, pp);
+  LoadClassById(result, TMP, pp);
 }
 
 
-void Assembler::CompareClassId(Register object,
-                               intptr_t class_id) {
-  LoadClassId(TMP, object);
-  CompareImmediate(TMP, class_id, PP);
+void Assembler::CompareClassId(
+    Register object, intptr_t class_id, Register pp) {
+  LoadClassId(TMP, object, pp);
+  CompareImmediate(TMP, class_id, pp);
 }
 
 
 // Frame entry and exit.
 void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
   // Reserve space for arguments and align frame before entering
   // the C++ world.
   AddImmediate(SP, SP, -frame_space, kNoPP);
   if (OS::ActivationFrameAlignment() > 1) {
     mov(TMP, SP);  // SP can't be register operand of andi.
@@ skipping 61 matching lines @@
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate. We must also set up the pool pointer for the function.
 void Assembler::EnterOsrFrame(intptr_t extra_size, Register new_pp) {
   Comment("EnterOsrFrame");
   adr(TMP, -CodeSize());
 
-  StoreToOffset(TMP, FP, kPcMarkerSlotFromFp * kWordSize);
+  StoreToOffset(TMP, FP, kPcMarkerSlotFromFp * kWordSize, kNoPP);
 
   // Setup pool pointer for this dart function.
   if (new_pp == kNoPP) {
     LoadPoolPointer(PP);
   } else {
     mov(PP, new_pp);
   }
 
   if (extra_size > 0) {
     AddImmediate(SP, SP, -extra_size, PP);
   }
 }
 
 
 void Assembler::LeaveDartFrame() {
   // Restore and untag PP.
-  LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize);
+  LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize, kNoPP);
   sub(PP, PP, Operand(kHeapObjectTag));
   LeaveFrame();
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_size) {
   EnterFrame(0);
 
   // Store fpu registers with the lowest register number at the lowest
   // address.
@@ skipping 62 matching lines @@
   Push(ZR);  // Push 0 in the saved PC area for stub frames.
   TagAndPushPP();  // Save caller's pool pointer
   if (load_pp) {
     LoadPoolPointer(PP);
   }
 }
 
 
 void Assembler::LeaveStubFrame() {
   // Restore and untag PP.
-  LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize);
+  LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize, kNoPP);
   sub(PP, PP, Operand(kHeapObjectTag));
   LeaveFrame();
 }
 
 
 void Assembler::UpdateAllocationStats(intptr_t cid,
                                       Register temp_reg,
                                       Register pp,
                                       Heap::Space space) {
   ASSERT(temp_reg != kNoRegister);
@@ skipping 108 matching lines @@
     ASSERT(instance_size >= kHeapObjectTag);
     AddImmediate(
         instance_reg, instance_reg, -instance_size + kHeapObjectTag, pp);
     UpdateAllocationStats(cls.id(), temp_reg, pp);
 
     uword tags = 0;
     tags = RawObject::SizeTag::update(instance_size, tags);
     ASSERT(cls.id() != kIllegalCid);
     tags = RawObject::ClassIdTag::update(cls.id(), tags);
     LoadImmediate(TMP, tags, pp);
-    StoreFieldToOffset(TMP, instance_reg, Object::tags_offset());
+    StoreFieldToOffset(TMP, instance_reg, Object::tags_offset(), pp);
   } else {
     b(failure);
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64