Adds single-precision and SIMD load/store to arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 531 matching lines @@
     if (a.type() == Address::PCOffset) {
       ASSERT(sz == kDoubleWord);
       EmitLoadRegLiteral(LDRpc, rt, a, sz);
     } else {
       // If we are doing pre-/post-indexing, and the base and result registers
       // are the same, then the result of the load will be clobbered by the
       // writeback, which is unlikely to be useful.
       ASSERT(((a.type() != Address::PreIndex) &&
               (a.type() != Address::PostIndex)) ||
              (rt != a.base()));
-      EmitLoadStoreReg(LDR, rt, a, sz);
+      if (IsSignedOperand(sz)) {
+        EmitLoadStoreReg(LDRS, rt, a, sz);
+      } else {
+        EmitLoadStoreReg(LDR, rt, a, sz);
+      }
     }
   }
   void str(Register rt, Address a, OperandSize sz = kDoubleWord) {
     EmitLoadStoreReg(STR, rt, a, sz);
   }
 
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitCoditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
   }
@@ skipping 97 matching lines @@
   }
   void fabsd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FABSD, vd, vn);
   }
   void fnegd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FNEGD, vd, vn);
   }
   void fsqrtd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FSQRTD, vd, vn);
   }
+  void fcvtsd(VRegister vd, VRegister vn) {
+    EmitFPOneSourceOp(FCVTSD, vd, vn);
+  }
+  void fcvtds(VRegister vd, VRegister vn) {
+    EmitFPOneSourceOp(FCVTDS, vd, vn);
+  }
+  void fldrq(VRegister vt, Address a) {
+    ASSERT(a.type() != Address::PCOffset);
+    EmitLoadStoreReg(FLDRQ, static_cast<Register>(vt), a, kByte);
+  }
+  void fstrq(VRegister vt, Address a) {
+    ASSERT(a.type() != Address::PCOffset);
+    EmitLoadStoreReg(FSTRQ, static_cast<Register>(vt), a, kByte);
+  }
   void fldrd(VRegister vt, Address a) {
     ASSERT(a.type() != Address::PCOffset);
-    EmitLoadStoreReg(FLDR, static_cast<Register>(vt), a, kDoubleWord);
+    EmitLoadStoreReg(FLDR, static_cast<Register>(vt), a, kDWord);
   }
   void fstrd(VRegister vt, Address a) {
     ASSERT(a.type() != Address::PCOffset);
-    EmitLoadStoreReg(FSTR, static_cast<Register>(vt), a, kDoubleWord);
+    EmitLoadStoreReg(FSTR, static_cast<Register>(vt), a, kDWord);
+  }
+  void fldrs(VRegister vt, Address a) {
+    ASSERT(a.type() != Address::PCOffset);
+    EmitLoadStoreReg(FLDR, static_cast<Register>(vt), a, kSWord);
+  }
+  void fstrs(VRegister vt, Address a) {
+    ASSERT(a.type() != Address::PCOffset);
+    EmitLoadStoreReg(FSTR, static_cast<Register>(vt), a, kSWord);
   }
   void fcmpd(VRegister vn, VRegister vm) {
     EmitFPCompareOp(FCMPD, vn, vm);
   }
   void fcmpzd(VRegister vn) {
     EmitFPCompareOp(FCMPZD, vn, V0);
   }
   void fmuld(VRegister vd, VRegister vn, VRegister vm) {
     EmitFPTwoSourceOp(FMULD, vd, vn, vm);
   }
@@ skipping 121 matching lines @@
 
   void LoadFromOffset(Register dest, Register base, int32_t offset,
                       OperandSize sz = kDoubleWord);
   void LoadFieldFromOffset(Register dest, Register base, int32_t offset) {
     LoadFromOffset(dest, base, offset - kHeapObjectTag);
   }
   void LoadDFromOffset(VRegister dest, Register base, int32_t offset);
   void LoadDFieldFromOffset(VRegister dest, Register base, int32_t offset) {
     LoadDFromOffset(dest, base, offset - kHeapObjectTag);
   }
+  void LoadQFromOffset(VRegister dest, Register base, int32_t offset);
+  void LoadQFieldFromOffset(VRegister dest, Register base, int32_t offset) {
+    LoadQFromOffset(dest, base, offset - kHeapObjectTag);
+  }
 
   void StoreToOffset(Register src, Register base, int32_t offset,
                      OperandSize sz = kDoubleWord);
   void StoreFieldToOffset(Register src, Register base, int32_t offset) {
     StoreToOffset(src, base, offset - kHeapObjectTag);
   }
   void StoreDToOffset(VRegister src, Register base, int32_t offset);
   void StoreDFieldToOffset(VRegister src, Register base, int32_t offset) {
     StoreDToOffset(src, base, offset - kHeapObjectTag);
   }
+  void StoreQToOffset(VRegister src, Register base, int32_t offset);
+  void StoreQFieldToOffset(VRegister src, Register base, int32_t offset) {
+    StoreQToOffset(src, base, offset - kHeapObjectTag);
+  }
 
   // Storing into an object.
   void StoreIntoObject(Register object,
                        const Address& dest,
                        Register value,
                        bool can_value_be_smi = true);
+  void StoreIntoObjectOffset(Register object,
+                             int32_t offset,
+                             Register value,
+                             bool can_value_be_smi = true);
   void StoreIntoObjectNoBarrier(Register object,
                                 const Address& dest,
                                 Register value);
+  void StoreIntoObjectOffsetNoBarrier(Register object,
+                                      int32_t offset,
+                                      Register value);
   void StoreIntoObjectNoBarrier(Register object,
                                 const Address& dest,
                                 const Object& value);
+  void StoreIntoObjectOffsetNoBarrier(Register object,
+                                      int32_t offset,
+                                      const Object& value);
 
   // Object pool, loading from pool, etc.
   void LoadPoolPointer(Register pp);
 
   // Index of constant pool entries pointing to debugger stubs.
   static const int kBreakpointRuntimeCPIndex = 5;
 
   enum Patchability {
     kPatchable,
     kNotPatchable,
@@ skipping 295 matching lines @@
         (static_cast<int32_t>(hw_idx) << kHWShift) |
         (static_cast<int32_t>(imm) << kImm16Shift);
     Emit(encoding);
   }
 
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const Register crt = ConcreteRegister(rt);
     const int32_t size = Log2OperandSizeBytes(sz);
     const int32_t encoding =
-        op | (size << kSzShift) |
+        op | ((size & 0x3) << kSzShift) |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitLoadRegLiteral(LoadRegLiteralOp op, Register rt, Address a,
                           OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT((rt != SP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
@@ skipping 120 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_