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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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161 #else | 161 #else |
162 // A patched return sequence is: | 162 // A patched return sequence is: |
163 // mov lr, pc | 163 // mov lr, pc |
164 // ldr pc, [pc, #-4] | 164 // ldr pc, [pc, #-4] |
165 return (current_instr == kMovLrPc) | 165 return (current_instr == kMovLrPc) |
166 && ((next_instr & kLdrPCMask) == kLdrPCPattern); | 166 && ((next_instr & kLdrPCMask) == kLdrPCPattern); |
167 #endif | 167 #endif |
168 } | 168 } |
169 | 169 |
170 | 170 |
| 171 bool RelocInfo::IsPatchedDebugBreakSlotSequence() { |
| 172 Instr current_instr = Assembler::instr_at(pc_); |
| 173 return !Assembler::IsNop(current_instr, 2); |
| 174 } |
| 175 |
| 176 |
171 void RelocInfo::Visit(ObjectVisitor* visitor) { | 177 void RelocInfo::Visit(ObjectVisitor* visitor) { |
172 RelocInfo::Mode mode = rmode(); | 178 RelocInfo::Mode mode = rmode(); |
173 if (mode == RelocInfo::EMBEDDED_OBJECT) { | 179 if (mode == RelocInfo::EMBEDDED_OBJECT) { |
174 visitor->VisitPointer(target_object_address()); | 180 visitor->VisitPointer(target_object_address()); |
175 } else if (RelocInfo::IsCodeTarget(mode)) { | 181 } else if (RelocInfo::IsCodeTarget(mode)) { |
176 visitor->VisitCodeTarget(this); | 182 visitor->VisitCodeTarget(this); |
177 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { | 183 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { |
178 visitor->VisitExternalReference(target_reference_address()); | 184 visitor->VisitExternalReference(target_reference_address()); |
179 #ifdef ENABLE_DEBUGGER_SUPPORT | 185 #ifdef ENABLE_DEBUGGER_SUPPORT |
180 } else if (Debug::has_break_points() && | 186 } else if (Debug::has_break_points() && |
181 RelocInfo::IsJSReturn(mode) && | 187 (RelocInfo::IsJSReturn(mode) && |
182 IsPatchedReturnSequence()) { | 188 IsPatchedReturnSequence()) || |
| 189 (RelocInfo::IsDebugBreakSlot(mode) && |
| 190 IsPatchedDebugBreakSlotSequence())) { |
183 visitor->VisitDebugTarget(this); | 191 visitor->VisitDebugTarget(this); |
184 #endif | 192 #endif |
185 } else if (mode == RelocInfo::RUNTIME_ENTRY) { | 193 } else if (mode == RelocInfo::RUNTIME_ENTRY) { |
186 visitor->VisitRuntimeEntry(this); | 194 visitor->VisitRuntimeEntry(this); |
187 } | 195 } |
188 } | 196 } |
189 | 197 |
190 | 198 |
191 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { | 199 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { |
192 rm_ = no_reg; | 200 rm_ = no_reg; |
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292 // CPU::FlushICache(pc, sizeof(target)); | 300 // CPU::FlushICache(pc, sizeof(target)); |
293 // However, on ARM, no instruction was actually patched by the assignment | 301 // However, on ARM, no instruction was actually patched by the assignment |
294 // above; the target address is not part of an instruction, it is patched in | 302 // above; the target address is not part of an instruction, it is patched in |
295 // the constant pool and is read via a data access; the instruction accessing | 303 // the constant pool and is read via a data access; the instruction accessing |
296 // this address in the constant pool remains unchanged. | 304 // this address in the constant pool remains unchanged. |
297 } | 305 } |
298 | 306 |
299 } } // namespace v8::internal | 307 } } // namespace v8::internal |
300 | 308 |
301 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ | 309 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ |
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