s390: use new mul instruction

src/s390/simulator-s390.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_S390
 
@@ skipping 967 matching lines @@
   EvalTable[SAL] = &Simulator::Evaluate_SAL;
   EvalTable[RSCH] = &Simulator::Evaluate_RSCH;
   EvalTable[STCRW] = &Simulator::Evaluate_STCRW;
   EvalTable[STCPS] = &Simulator::Evaluate_STCPS;
   EvalTable[RCHP] = &Simulator::Evaluate_RCHP;
   EvalTable[SCHM] = &Simulator::Evaluate_SCHM;
   EvalTable[CKSM] = &Simulator::Evaluate_CKSM;
   EvalTable[SAR] = &Simulator::Evaluate_SAR;
   EvalTable[EAR] = &Simulator::Evaluate_EAR;
   EvalTable[MSR] = &Simulator::Evaluate_MSR;
+  EvalTable[MSRKC] = &Simulator::Evaluate_MSRKC;
   EvalTable[MVST] = &Simulator::Evaluate_MVST;
   EvalTable[CUSE] = &Simulator::Evaluate_CUSE;
   EvalTable[SRST] = &Simulator::Evaluate_SRST;
   EvalTable[XSCH] = &Simulator::Evaluate_XSCH;
   EvalTable[STCKE] = &Simulator::Evaluate_STCKE;
   EvalTable[STCKF] = &Simulator::Evaluate_STCKF;
   EvalTable[SRNM] = &Simulator::Evaluate_SRNM;
   EvalTable[STFPC] = &Simulator::Evaluate_STFPC;
   EvalTable[LFPC] = &Simulator::Evaluate_LFPC;
   EvalTable[TRE] = &Simulator::Evaluate_TRE;
@@ skipping 153 matching lines @@
   EvalTable[LTGR] = &Simulator::Evaluate_LTGR;
   EvalTable[LCGR] = &Simulator::Evaluate_LCGR;
   EvalTable[LGR] = &Simulator::Evaluate_LGR;
   EvalTable[LGBR] = &Simulator::Evaluate_LGBR;
   EvalTable[LGHR] = &Simulator::Evaluate_LGHR;
   EvalTable[AGR] = &Simulator::Evaluate_AGR;
   EvalTable[SGR] = &Simulator::Evaluate_SGR;
   EvalTable[ALGR] = &Simulator::Evaluate_ALGR;
   EvalTable[SLGR] = &Simulator::Evaluate_SLGR;
   EvalTable[MSGR] = &Simulator::Evaluate_MSGR;
+  EvalTable[MSGRKC] = &Simulator::Evaluate_MSGRKC;
   EvalTable[DSGR] = &Simulator::Evaluate_DSGR;
   EvalTable[LRVGR] = &Simulator::Evaluate_LRVGR;
   EvalTable[LPGFR] = &Simulator::Evaluate_LPGFR;
   EvalTable[LNGFR] = &Simulator::Evaluate_LNGFR;
   EvalTable[LTGFR] = &Simulator::Evaluate_LTGFR;
   EvalTable[LCGFR] = &Simulator::Evaluate_LCGFR;
   EvalTable[LGFR] = &Simulator::Evaluate_LGFR;
   EvalTable[LLGFR] = &Simulator::Evaluate_LLGFR;
   EvalTable[LLGTR] = &Simulator::Evaluate_LLGTR;
   EvalTable[AGFR] = &Simulator::Evaluate_AGFR;
@@ skipping 7293 matching lines @@
 
 EVALUATE(MSR) {
   DCHECK_OPCODE(MSR);
   DECODE_RRE_INSTRUCTION(r1, r2);
   int32_t r1_val = get_low_register<int32_t>(r1);
   int32_t r2_val = get_low_register<int32_t>(r2);
   set_low_register(r1, r1_val * r2_val);
   return length;
 }
 
+EVALUATE(MSRKC) {
+  DCHECK_OPCODE(MSRKC);
+  DECODE_RRF_A_INSTRUCTION(r1, r2, r3);
+  int32_t r2_val = get_low_register<int32_t>(r2);
+  int32_t r3_val = get_low_register<int32_t>(r3);
+  int64_t result64 =
+      static_cast<int64_t>(r2_val) * static_cast<int64_t>(r3_val);
+  int32_t result32 = static_cast<int32_t>(result64);
+  bool isOF = (static_cast<int64_t>(result32) != result64);
+  SetS390ConditionCode<int32_t>(result32, 0);
+  SetS390OverflowCode(isOF);
+  set_low_register(r1, result32);
+  return length;
+}
+
 EVALUATE(MVST) {
   UNIMPLEMENTED();
   USE(instr);
   return 0;
 }
 
 EVALUATE(CUSE) {
   UNIMPLEMENTED();
   USE(instr);
   return 0;
@@ skipping 1505 matching lines @@
 
 EVALUATE(MSGR) {
   DCHECK_OPCODE(MSGR);
   DECODE_RRE_INSTRUCTION(r1, r2);
   int64_t r1_val = get_register(r1);
   int64_t r2_val = get_register(r2);
   set_register(r1, r1_val * r2_val);
   return length;
 }
 
+EVALUATE(MSGRKC) {
+  DCHECK_OPCODE(MSGRKC);
+  DECODE_RRF_A_INSTRUCTION(r1, r2, r3);
+  int64_t r2_val = get_register(r2);
+  int64_t r3_val = get_register(r3);
+  volatile int64_t result64 = r2_val * r3_val;
+  bool isOF = ((r2_val == -1 && result64 == (static_cast<int64_t>(1L) << 63)) ||
+               (r2_val != 0 && result64 / r2_val != r3_val));
+  SetS390ConditionCode<int64_t>(result64, 0);
+  SetS390OverflowCode(isOF);
+  set_register(r1, result64);
+  return length;
+}
+
 EVALUATE(DSGR) {
   DCHECK_OPCODE(DSGR);
   DECODE_RRE_INSTRUCTION(r1, r2);
 
   DCHECK(r1 % 2 == 0);
 
   int64_t dividend = get_register(r1 + 1);
   int64_t divisor = get_register(r2);
   set_register(r1, dividend % divisor);
   set_register(r1 + 1, dividend / divisor);
@@ skipping 2806 matching lines @@
   return 0;
 }
 
 #undef EVALUATE
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 #endif  // V8_TARGET_ARCH_S390