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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_S390 | 8 #if V8_TARGET_ARCH_S390 |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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3357 } | 3357 } |
3358 } | 3358 } |
3359 | 3359 |
3360 void MacroAssembler::Mul64(Register dst, Register src1) { msgr(dst, src1); } | 3360 void MacroAssembler::Mul64(Register dst, Register src1) { msgr(dst, src1); } |
3361 | 3361 |
3362 void MacroAssembler::Mul64(Register dst, const Operand& src1) { | 3362 void MacroAssembler::Mul64(Register dst, const Operand& src1) { |
3363 msgfi(dst, src1); | 3363 msgfi(dst, src1); |
3364 } | 3364 } |
3365 | 3365 |
3366 void MacroAssembler::Mul(Register dst, Register src1, Register src2) { | 3366 void MacroAssembler::Mul(Register dst, Register src1, Register src2) { |
3367 if (dst.is(src2)) { | 3367 if (CpuFeatures::IsSupported(MISC_INSTR_EXT2)) { |
3368 MulP(dst, src1); | 3368 MulPWithCondition(dst, src1, src2); |
3369 } else if (dst.is(src1)) { | |
3370 MulP(dst, src2); | |
3371 } else { | 3369 } else { |
3372 Move(dst, src1); | 3370 if (dst.is(src2)) { |
3373 MulP(dst, src2); | 3371 MulP(dst, src1); |
| 3372 } else if (dst.is(src1)) { |
| 3373 MulP(dst, src2); |
| 3374 } else { |
| 3375 Move(dst, src1); |
| 3376 MulP(dst, src2); |
| 3377 } |
3374 } | 3378 } |
3375 } | 3379 } |
3376 | 3380 |
3377 void MacroAssembler::DivP(Register dividend, Register divider) { | 3381 void MacroAssembler::DivP(Register dividend, Register divider) { |
3378 // have to make sure the src and dst are reg pairs | 3382 // have to make sure the src and dst are reg pairs |
3379 DCHECK(dividend.code() % 2 == 0); | 3383 DCHECK(dividend.code() % 2 == 0); |
3380 #if V8_TARGET_ARCH_S390X | 3384 #if V8_TARGET_ARCH_S390X |
3381 dsgr(dividend, divider); | 3385 dsgr(dividend, divider); |
3382 #else | 3386 #else |
3383 dr(dividend, divider); | 3387 dr(dividend, divider); |
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3495 } | 3499 } |
3496 | 3500 |
3497 void MacroAssembler::MulP(Register dst, Register src) { | 3501 void MacroAssembler::MulP(Register dst, Register src) { |
3498 #if V8_TARGET_ARCH_S390X | 3502 #if V8_TARGET_ARCH_S390X |
3499 msgr(dst, src); | 3503 msgr(dst, src); |
3500 #else | 3504 #else |
3501 msr(dst, src); | 3505 msr(dst, src); |
3502 #endif | 3506 #endif |
3503 } | 3507 } |
3504 | 3508 |
| 3509 void MacroAssembler::MulPWithCondition(Register dst, Register src1, |
| 3510 Register src2) { |
| 3511 CHECK(CpuFeatures::IsSupported(MISC_INSTR_EXT2)); |
| 3512 #if V8_TARGET_ARCH_S390X |
| 3513 msgrkc(dst, src1, src2); |
| 3514 #else |
| 3515 msrkc(dst, src1, src2); |
| 3516 #endif |
| 3517 } |
| 3518 |
3505 void MacroAssembler::MulP(Register dst, const MemOperand& opnd) { | 3519 void MacroAssembler::MulP(Register dst, const MemOperand& opnd) { |
3506 #if V8_TARGET_ARCH_S390X | 3520 #if V8_TARGET_ARCH_S390X |
3507 if (is_uint16(opnd.offset())) { | 3521 if (is_uint16(opnd.offset())) { |
3508 ms(dst, opnd); | 3522 ms(dst, opnd); |
3509 } else if (is_int20(opnd.offset())) { | 3523 } else if (is_int20(opnd.offset())) { |
3510 msy(dst, opnd); | 3524 msy(dst, opnd); |
3511 } else { | 3525 } else { |
3512 UNIMPLEMENTED(); | 3526 UNIMPLEMENTED(); |
3513 } | 3527 } |
3514 #else | 3528 #else |
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5352 } | 5366 } |
5353 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); | 5367 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); |
5354 ExtractBit(r0, dividend, 31); | 5368 ExtractBit(r0, dividend, 31); |
5355 AddP(result, r0); | 5369 AddP(result, r0); |
5356 } | 5370 } |
5357 | 5371 |
5358 } // namespace internal | 5372 } // namespace internal |
5359 } // namespace v8 | 5373 } // namespace v8 |
5360 | 5374 |
5361 #endif // V8_TARGET_ARCH_S390 | 5375 #endif // V8_TARGET_ARCH_S390 |
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