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Issue 2691893002: s390: use new mul instruction (Closed)
Patch Set: fix comment Created 3 years, 10 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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768 break; 768 break;
769 case LTGFR: 769 case LTGFR:
770 Format(instr, "ltgfr\t'r5,'r6"); 770 Format(instr, "ltgfr\t'r5,'r6");
771 break; 771 break;
772 case LCGR: 772 case LCGR:
773 Format(instr, "lcgr\t'r5,'r6"); 773 Format(instr, "lcgr\t'r5,'r6");
774 break; 774 break;
775 case MSR: 775 case MSR:
776 Format(instr, "msr\t'r5,'r6"); 776 Format(instr, "msr\t'r5,'r6");
777 break; 777 break;
778 case MSRKC:
779 Format(instr, "msrkc\t'r5,'r6,'r3");
780 break;
778 case LGBR: 781 case LGBR:
779 Format(instr, "lgbr\t'r5,'r6"); 782 Format(instr, "lgbr\t'r5,'r6");
780 break; 783 break;
781 case LGHR: 784 case LGHR:
782 Format(instr, "lghr\t'r5,'r6"); 785 Format(instr, "lghr\t'r5,'r6");
783 break; 786 break;
784 case MSGR: 787 case MSGR:
785 Format(instr, "msgr\t'r5,'r6"); 788 Format(instr, "msgr\t'r5,'r6");
786 break; 789 break;
790 case MSGRKC:
791 Format(instr, "msgrkc\t'r5,'r6,'r3");
792 break;
787 case DSGR: 793 case DSGR:
788 Format(instr, "dsgr\t'r5,'r6"); 794 Format(instr, "dsgr\t'r5,'r6");
789 break; 795 break;
790 case DSGFR: 796 case DSGFR:
791 Format(instr, "dsgfr\t'r5,'r6"); 797 Format(instr, "dsgfr\t'r5,'r6");
792 break; 798 break;
793 case MSGFR: 799 case MSGFR:
794 Format(instr, "msgfr\t'r5,'r6"); 800 Format(instr, "msgfr\t'r5,'r6");
795 break; 801 break;
796 case LZDR: 802 case LZDR:
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1531 byte* prev_pc = pc; 1537 byte* prev_pc = pc;
1532 pc += d.InstructionDecode(buffer, pc); 1538 pc += d.InstructionDecode(buffer, pc);
1533 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), 1539 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc),
1534 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1540 *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1535 } 1541 }
1536 } 1542 }
1537 1543
1538 } // namespace disasm 1544 } // namespace disasm
1539 1545
1540 #endif // V8_TARGET_ARCH_S390 1546 #endif // V8_TARGET_ARCH_S390
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