s390: use new mul instruction

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 148 matching lines @@
       supported_ |= (1u << GENERAL_INSTR_EXT);
     }
     // Test for Floating Point Extension Facility - Bit 37
     if (facilities[0] & (one << (63 - 37))) {
       supported_ |= (1u << FLOATING_POINT_EXT);
     }
     // Test for Vector Facility - Bit 129
     if (facilities[2] & (one << (63 - (129 - 128)))) {
       supported_ |= (1u << VECTOR_FACILITY);
     }
+    // Test for Miscellaneous Instruction Extension Facility - Bit 58
+    if (facilities[0] & (1lu << (63 - 58))) {
+      supported_ |= (1u << MISC_INSTR_EXT2);
+    }
   }
 #else
   // All distinct ops instructions can be simulated
   supported_ |= (1u << DISTINCT_OPS);
   // RISBG can be simulated
   supported_ |= (1u << GENERAL_INSTR_EXT);
-
   supported_ |= (1u << FLOATING_POINT_EXT);
+  supported_ |= (1u << MISC_INSTR_EXT2);
   USE(performSTFLE);  // To avoid assert
   supported_ |= (1u << VECTOR_FACILITY);
 #endif
   supported_ |= (1u << FPU);
 }
 
 void CpuFeatures::PrintTarget() {
   const char* s390_arch = NULL;
 
 #if V8_TARGET_ARCH_S390X
   s390_arch = "s390x";
 #else
   s390_arch = "s390";
 #endif
 
   printf("target %s\n", s390_arch);
 }
 
 void CpuFeatures::PrintFeatures() {
   printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
   printf("FPU_EXT=%d\n", CpuFeatures::IsSupported(FLOATING_POINT_EXT));
   printf("GENERAL_INSTR=%d\n", CpuFeatures::IsSupported(GENERAL_INSTR_EXT));
   printf("DISTINCT_OPS=%d\n", CpuFeatures::IsSupported(DISTINCT_OPS));
   printf("VECTOR_FACILITY=%d\n", CpuFeatures::IsSupported(VECTOR_FACILITY));
+  printf("MISC_INSTR_EXT2=%d\n", CpuFeatures::IsSupported(MISC_INSTR_EXT2));
 }
 
 Register ToRegister(int num) {
   DCHECK(num >= 0 && num < kNumRegisters);
   const Register kRegisters[] = {r0, r1, r2,  r3, r4, r5,  r6,  r7,
                                  r8, r9, r10, fp, ip, r13, r14, sp};
   return kRegisters[num];
 }
 
 // -----------------------------------------------------------------------------
@@ skipping 1292 matching lines @@
 }
 
 // ----------------------------
 // 32-bit Multiply Instructions
 // ----------------------------
 // Multiply Halfword Immediate (32)
 void Assembler::mhi(Register r1, const Operand& opnd) {
   ri_form(MHI, r1, opnd);
 }
 
+// Multiply Single Register (32)
+void Assembler::msrkc(Register r1, Register r2, Register r3) {
+  rrf1_form(MSRKC, r1, r2, r3);
+}
+
+// Multiply Single Register (64)
+void Assembler::msgrkc(Register r1, Register r2, Register r3) {
+  rrf1_form(MSGRKC, r1, r2, r3);
+}
+
 // ----------------------------
 // 64-bit Multiply Instructions
 // ----------------------------
 // Multiply Halfword Immediate (64)
 void Assembler::mghi(Register r1, const Operand& opnd) {
   ri_form(MGHI, r1, opnd);
 }
 
 // --------------------
 // Bitwise Instructions
@@ skipping 575 matching lines @@
                             SKIP_ICACHE_FLUSH);
     }
 
     reloc_info_writer.Write(&rinfo);
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390