Adds assert to mips assembler macros.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 750 matching lines @@
   // from the other registers is needed.
   void AdduDetectOverflow(Register rd, Register rs, Register rt, Register ro,
                           Register scratch = kNoRegister);
 
   // ro must be different from rd and rs.
   // rd and ro must not be TMP.
   // If rd and rs are the same, a scratch register different from the other
   // registers is needed.
   void AddImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
                                   Register ro, Register scratch = kNoRegister) {
+    ASSERT(!in_delay_slot_);
     LoadImmediate(rd, imm);
     AdduDetectOverflow(rd, rs, rd, ro, scratch);
   }
 
   // Subtraction of rt from rs (rs - rt) with the result placed in rd.
   // After, ro < 0 if there was signed overflow, ro >= 0 otherwise.
   // None of rd, rs, rt, or ro may be TMP.
   // ro must be different from the other registers.
   void SubuDetectOverflow(Register rd, Register rs, Register rt, Register ro);
 
   // ro must be different from rd and rs.
   // None of rd, rs, rt, or ro may be TMP.
   void SubImmediateDetectOverflow(Register rd, Register rs, int32_t imm,
                                   Register ro) {
+    ASSERT(!in_delay_slot_);
     LoadImmediate(rd, imm);
     SubuDetectOverflow(rd, rs, rd, ro);
   }
 
   void Branch(const ExternalLabel* label) {
+    ASSERT(!in_delay_slot_);
     LoadImmediate(TMP, label->address());
     jr(TMP);
   }
 
   void BranchPatchable(const ExternalLabel* label) {
+    ASSERT(!in_delay_slot_);
     const uint16_t low = Utils::Low16Bits(label->address());
     const uint16_t high = Utils::High16Bits(label->address());
     lui(T9, Immediate(high));
     ori(T9, T9, Immediate(low));
     jr(T9);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
   void BranchLink(const ExternalLabel* label) {
+    ASSERT(!in_delay_slot_);
     LoadImmediate(T9, label->address());
     jalr(T9);
   }
 
   void BranchLinkPatchable(const ExternalLabel* label) {
+    ASSERT(!in_delay_slot_);
     const int32_t offset =
         Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
     LoadWordFromPoolOffset(T9, offset);
     jalr(T9);
     delay_slot_available_ = false;  // CodePatcher expects a nop.
   }
 
   void Drop(intptr_t stack_elements) {
     ASSERT(stack_elements >= 0);
     if (stack_elements > 0) {
       addiu(SP, SP, Immediate(stack_elements * kWordSize));
     }
   }
 
   void LoadPoolPointer() {
+    ASSERT(!in_delay_slot_);
     GetNextPC(TMP);  // TMP gets the address of the next instruction.
     const intptr_t object_pool_pc_dist =
         Instructions::HeaderSize() - Instructions::object_pool_offset() +
         CodeSize();
     lw(PP, Address(TMP, -object_pool_pc_dist));
   }
 
   void LoadImmediate(Register rd, int32_t value) {
+    ASSERT(!in_delay_slot_);
     if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       const uint16_t low = Utils::Low16Bits(value);
       const uint16_t high = Utils::High16Bits(value);
       lui(rd, Immediate(high));
       ori(rd, rd, Immediate(low));
     }
   }
 
   void LoadImmediate(DRegister rd, double value) {
+    ASSERT(!in_delay_slot_);
     FRegister frd = static_cast<FRegister>(rd * 2);
     const int64_t ival = bit_cast<uint64_t, double>(value);
     const int32_t low = Utils::Low32Bits(ival);
     const int32_t high = Utils::High32Bits(ival);
     if (low != 0) {
       LoadImmediate(TMP, low);
       mtc1(TMP, frd);
     } else {
       mtc1(ZR, frd);
     }
 
     if (high != 0) {
       LoadImmediate(TMP, high);
       mtc1(TMP, static_cast<FRegister>(frd + 1));
     } else {
       mtc1(ZR, static_cast<FRegister>(frd + 1));
     }
   }
 
   void LoadImmediate(FRegister rd, float value) {
+    ASSERT(!in_delay_slot_);
     const int32_t ival = bit_cast<int32_t, float>(value);
     if (ival == 0) {
       mtc1(ZR, rd);
     } else {
       LoadImmediate(TMP, ival);
       mtc1(TMP, rd);
     }
   }
 
   void AddImmediate(Register rd, Register rs, int32_t value) {
+    ASSERT(!in_delay_slot_);
     if ((value == 0) && (rd == rs)) return;
     // If value is 0, we still want to move rs to rd if they aren't the same.
     if (Utils::IsInt(kImmBits, value)) {
       addiu(rd, rs, Immediate(value));
     } else {
       LoadImmediate(TMP, value);
       addu(rd, rs, TMP);
     }
   }
 
   void AddImmediate(Register rd, int32_t value) {
+    ASSERT(!in_delay_slot_);
     AddImmediate(rd, rd, value);
   }
 
   void AndImmediate(Register rd, Register rs, int32_t imm) {
+    ASSERT(!in_delay_slot_);
     if (imm == 0) {
       mov(rd, ZR);
       return;
     }
 
     if (Utils::IsUint(kImmBits, imm)) {
       andi(rd, rs, Immediate(imm));
     } else {
       LoadImmediate(TMP, imm);
       and_(rd, rs, TMP);
     }
   }
 
   void BranchEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       beq(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       beq(rd, CMPRES2, l);
     }
   }
 
   void BranchEqual(Register rd, const Object& object, Label* l) {
+    ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadObject(CMPRES2, object);
     beq(rd, CMPRES2, l);
   }
 
   void BranchNotEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       bne(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       bne(rd, CMPRES2, l);
     }
   }
 
   void BranchNotEqual(Register rd, const Object& object, Label* l) {
+    ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadObject(CMPRES2, object);
     bne(rd, CMPRES2, l);
   }
 
   void BranchSignedGreater(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     slt(CMPRES2, rs, rd);  // CMPRES2 = rd > rs ? 1 : 0.
     bne(CMPRES2, ZR, l);
   }
 
   void BranchSignedGreater(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       bgtz(rd, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       BranchSignedGreater(rd, CMPRES2, l);
     }
   }
 
   void BranchUnsignedGreater(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rs, rd);
     bne(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreater(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       BranchNotEqual(rd, 0, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       BranchUnsignedGreater(rd, CMPRES2, l);
     }
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     slt(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);  // If CMPRES2 = 0, then rd >= rs.
   }
 
   void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       bgez(rd, l);
     } else {
       if (Utils::IsInt(kImmBits, value)) {
         slti(CMPRES2, rd, Immediate(value));
         beq(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
         LoadImmediate(CMPRES2, value);
         BranchSignedGreaterEqual(rd, CMPRES2, l);
       }
     }
   }
 
   void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);
   }
 
   void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       b(l);
     } else {
       if (Utils::IsUint(kImmBits, value)) {
         sltiu(CMPRES2, rd, Immediate(value));
         beq(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
         LoadImmediate(CMPRES2, value);
         BranchUnsignedGreaterEqual(rd, CMPRES2, l);
       }
     }
   }
 
   void BranchSignedLess(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     BranchSignedGreater(rs, rd, l);
   }
 
   void BranchSignedLess(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       bltz(rd, l);
     } else {
       if (Utils::IsInt(kImmBits, value)) {
         slti(CMPRES2, rd, Immediate(value));
         bne(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
         LoadImmediate(CMPRES2, value);
         BranchSignedGreater(CMPRES2, rd, l);
       }
     }
   }
 
   void BranchUnsignedLess(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     BranchUnsignedGreater(rs, rd, l);
   }
 
   void BranchUnsignedLess(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     ASSERT(value != 0);
     if (Utils::IsUint(kImmBits, value)) {
       sltiu(CMPRES2, rd, Immediate(value));
       bne(CMPRES2, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       BranchUnsignedGreater(CMPRES2, rd, l);
     }
   }
 
   void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     BranchSignedGreaterEqual(rs, rd, l);
   }
 
   void BranchSignedLessEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     if (value == 0) {
       blez(rd, l);
     } else {
       ASSERT(rd != CMPRES2);
       LoadImmediate(CMPRES2, value);
       BranchSignedGreaterEqual(CMPRES2, rd, l);
     }
   }
 
   void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
     BranchUnsignedGreaterEqual(rs, rd, l);
   }
 
   void BranchUnsignedLessEqual(Register rd, int32_t value, Label* l) {
+    ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadImmediate(CMPRES2, value);
     BranchUnsignedGreaterEqual(CMPRES2, rd, l);
   }
 
   void Push(Register rt) {
+    ASSERT(!in_delay_slot_);
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
+    ASSERT(!in_delay_slot_);
     lw(rt, Address(SP));
     addiu(SP, SP, Immediate(kWordSize));
   }
 
   void Ret() {
     jr(RA);
   }
 
   void SmiTag(Register reg) {
     sll(reg, reg, kSmiTagSize);
   }
 
   void SmiUntag(Register reg) {
     sra(reg, reg, kSmiTagSize);
   }
 
   void LoadFromOffset(Register reg, Register base, int32_t offset) {
+    ASSERT(!in_delay_slot_);
     if (Utils::IsInt(kImmBits, offset)) {
       lw(reg, Address(base, offset));
     } else {
       LoadImmediate(TMP, offset);
       addu(TMP, base, TMP);
       lw(reg, Address(TMP, 0));
     }
   }
 
   void StoreToOffset(Register reg, Register base, int32_t offset) {
+    ASSERT(!in_delay_slot_);
     if (Utils::IsInt(kImmBits, offset)) {
       sw(reg, Address(base, offset));
     } else {
       LoadImmediate(TMP, offset);
       addu(TMP, base, TMP);
       sw(reg, Address(TMP, 0));
     }
   }
 
   void StoreDToOffset(DRegister reg, Register base, int32_t offset) {
+    ASSERT(!in_delay_slot_);
     FRegister lo = static_cast<FRegister>(reg * 2);
     FRegister hi = static_cast<FRegister>(reg * 2 + 1);
     swc1(lo, Address(base, offset));
     swc1(hi, Address(base, offset + kWordSize));
   }
 
   void LoadDFromOffset(DRegister reg, Register base, int32_t offset) {
+    ASSERT(!in_delay_slot_);
     FRegister lo = static_cast<FRegister>(reg * 2);
     FRegister hi = static_cast<FRegister>(reg * 2 + 1);
     lwc1(lo, Address(base, offset));
     lwc1(hi, Address(base, offset + kWordSize));
   }
 
   // dest gets the address of the following instruction. If temp is given,
   // RA is preserved using it as a temporary.
   void GetNextPC(Register dest, Register temp = kNoRegister);
 
@@ skipping 178 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_