Adds assert to mips assembler macros.

runtime/vm/assembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
@@ skipping 94 matching lines @@
     // If the offset loading instructions aren't there, we must have replaced
     // the far branch with a near one, and so these instructions should be NOPs.
     ASSERT((high == Instr::kNopInstruction) && (low == Instr::kNopInstruction));
   }
 
   virtual bool IsPointerOffset() const { return false; }
 };
 
 
 void Assembler::EmitFarJump(int32_t offset, bool link) {
+  ASSERT(!in_delay_slot_);
   ASSERT(use_far_branches());
   const uint16_t low = Utils::Low16Bits(offset);
   const uint16_t high = Utils::High16Bits(offset);
   buffer_.EmitFixup(new PatchFarJump());
   lui(T9, Immediate(high));
   ori(T9, T9, Immediate(low));
   if (link) {
     EmitRType(SPECIAL, T9, R0, RA, 0, JALR);
   } else {
     EmitRType(SPECIAL, T9, R0, R0, 0, JR);
@@ skipping 14 matching lines @@
     default:
       UNREACHABLE();
       break;
   }
   return BNE;
 }
 
 
 void Assembler::EmitFarBranch(Opcode b, Register rs, Register rt,
                               int32_t offset) {
+  ASSERT(!in_delay_slot_);
   EmitIType(b, rs, rt, 4);
   nop();
   EmitFarJump(offset, false);
 }
 
 
 static RtRegImm OppositeBranchNoLink(RtRegImm b) {
   switch (b) {
     case BLTZ: return BGEZ;
     case BGEZ: return BLTZ;
     case BLTZAL: return BGEZ;
     case BGEZAL: return BLTZ;
     default:
       UNREACHABLE();
       break;
   }
   return BLTZ;
 }
 
 
 void Assembler::EmitFarRegImmBranch(RtRegImm b, Register rs, int32_t offset) {
+  ASSERT(!in_delay_slot_);
   EmitRegImmType(REGIMM, rs, b, 4);
   nop();
   EmitFarJump(offset, (b == BLTZAL) || (b == BGEZAL));
 }
 
 
 void Assembler::EmitFarFpuBranch(bool kind, int32_t offset) {
+  ASSERT(!in_delay_slot_);
   const uint32_t b16 = kind ? (1 << 16) : 0;
   Emit(COP1 << kOpcodeShift | COP1_BC << kCop1SubShift | b16 | 4);
   nop();
   EmitFarJump(offset, false);
 }
 
 
 void Assembler::EmitBranch(Opcode b, Register rs, Register rt, Label* label) {
+  ASSERT(!in_delay_slot_);
   if (label->IsBound()) {
     // Relative destination from an instruction after the branch.
     const int32_t dest =
         label->Position() - (buffer_.Size() + Instr::kInstrSize);
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       EmitFarBranch(OppositeBranchOpcode(b), rs, rt, label->Position());
     } else {
       const uint16_t dest_off = EncodeBranchOffset(dest, 0);
       EmitIType(b, rs, rt, dest_off);
     }
   } else {
     const intptr_t position = buffer_.Size();
     if (use_far_branches()) {
       const uint32_t dest_off = label->position_;
       EmitFarBranch(b, rs, rt, dest_off);
     } else {
       const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
       EmitIType(b, rs, rt, dest_off);
     }
     label->LinkTo(position);
   }
 }
 
 
 void Assembler::EmitRegImmBranch(RtRegImm b, Register rs, Label* label) {
+  ASSERT(!in_delay_slot_);
   if (label->IsBound()) {
     // Relative destination from an instruction after the branch.
     const int32_t dest =
         label->Position() - (buffer_.Size() + Instr::kInstrSize);
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       EmitFarRegImmBranch(OppositeBranchNoLink(b), rs, label->Position());
     } else {
       const uint16_t dest_off = EncodeBranchOffset(dest, 0);
       EmitRegImmType(REGIMM, rs, b, dest_off);
     }
   } else {
     const intptr_t position = buffer_.Size();
     if (use_far_branches()) {
       const uint32_t dest_off = label->position_;
       EmitFarRegImmBranch(b, rs, dest_off);
     } else {
       const uint16_t dest_off = EncodeBranchOffset(label->position_, 0);
       EmitRegImmType(REGIMM, rs, b, dest_off);
     }
     label->LinkTo(position);
   }
 }
 
 
 void Assembler::EmitFpuBranch(bool kind, Label *label) {
+  ASSERT(!in_delay_slot_);
   const int32_t b16 = kind ? (1 << 16) : 0;  // Bit 16 set for branch on true.
   if (label->IsBound()) {
     // Relative destination from an instruction after the branch.
     const int32_t dest =
         label->Position() - (buffer_.Size() + Instr::kInstrSize);
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       EmitFarFpuBranch(kind, label->Position());
     } else {
       const uint16_t dest_off = EncodeBranchOffset(dest, 0);
       Emit(COP1 << kOpcodeShift |
@@ skipping 96 matching lines @@
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = DecodeBranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
   delay_slot_available_ = false;
 }
 
 
 void Assembler::LoadWordFromPoolOffset(Register rd, int32_t offset) {
+  ASSERT(!in_delay_slot_);
   ASSERT(rd != PP);
   if (Address::CanHoldOffset(offset)) {
     lw(rd, Address(PP, offset));
   } else {
     const int16_t offset_low = Utils::Low16Bits(offset);  // Signed.
     offset -= offset_low;
     const uint16_t offset_high = Utils::High16Bits(offset);  // Unsigned.
     if (offset_high != 0) {
       lui(rd, Immediate(offset_high));
       addu(rd, rd, PP);
       lw(rd, Address(rd, offset_low));
     } else {
       lw(rd, Address(PP, offset_low));
     }
   }
 }
 
 
 void Assembler::AdduDetectOverflow(Register rd, Register rs, Register rt,
                                    Register ro, Register scratch) {
+  ASSERT(!in_delay_slot_);
   ASSERT(rd != ro);
   ASSERT(rd != TMP);
   ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
 
   if ((rs == rt) && (rd == rs)) {
     ASSERT(scratch != kNoRegister);
     ASSERT(scratch != TMP);
     ASSERT(rd != scratch);
@@ skipping 20 matching lines @@
     addu(rd, rs, rt);
     xor_(ro, rd, rs);
     xor_(TMP, rd, rt);
     and_(ro, TMP, ro);
   }
 }
 
 
 void Assembler::SubuDetectOverflow(Register rd, Register rs, Register rt,
                                    Register ro) {
+  ASSERT(!in_delay_slot_);
   ASSERT(rd != ro);
   ASSERT(rd != TMP);
   ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
   ASSERT(rs != TMP);
   ASSERT(rt != TMP);
 
   // This happens with some crankshaft code. Since Subu works fine if
   // left == right, let's not make that restriction here.
@@ skipping 18 matching lines @@
   } else {
     subu(rd, rs, rt);
     xor_(ro, rd, rs);
     xor_(TMP, rs, rt);
     and_(ro, TMP, ro);
   }
 }
 
 
 void Assembler::LoadObject(Register rd, const Object& object) {
+  ASSERT(!in_delay_slot_);
   // Smis and VM heap objects are never relocated; do not use object pool.
   if (object.IsSmi()) {
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()));
   } else if (object.InVMHeap()) {
     // Make sure that class CallPattern is able to decode this load immediate.
     int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
     const uint16_t object_low = Utils::Low16Bits(object_raw);
     const uint16_t object_high = Utils::High16Bits(object_raw);
     lui(rd, Immediate(object_high));
     ori(rd, rd, Immediate(object_low));
@@ skipping 19 matching lines @@
     if (object_pool_.At(i) == obj.raw()) {
       return i;
     }
   }
   object_pool_.Add(obj, Heap::kOld);
   return object_pool_.Length() - 1;
 }
 
 
 void Assembler::PushObject(const Object& object) {
+  ASSERT(!in_delay_slot_);
   LoadObject(TMP, object);
   Push(TMP);
 }
 
 
 void Assembler::CompareObject(Register rd1, Register rd2,
                               Register rn, const Object& object) {
+  ASSERT(!in_delay_slot_);
   ASSERT(rn != TMP);
   ASSERT(rd1 != TMP);
   ASSERT(rd1 != rd2);
   LoadObject(TMP, object);
   slt(rd1, rn, TMP);
   slt(rd2, TMP, rn);
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
+  ASSERT(!in_delay_slot_);
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0), young_alignment);
 
   // Write-barrier triggers if the value is in the new space (has bit set) and
   // the object is in the old space (has bit cleared).
   // To check that, we compute value & ~object and skip the write barrier
   // if the bit is not set. We can't destroy the object.
   nor(TMP, ZR, object);
   and_(TMP, value, TMP);
   andi(CMPRES1, TMP, Immediate(kNewObjectAlignmentOffset));
   beq(CMPRES1, ZR, no_update);
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilter(Register object,
                                       Register value,
                                       Label* no_update) {
+  ASSERT(!in_delay_slot_);
   // For the value we are only interested in the new/old bit and the tag bit.
   // And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
   sll(TMP, value, kObjectAlignmentLog2 - 1);
   and_(TMP, value, TMP);
   // And the result with the negated space bit of the object.
   nor(CMPRES1, ZR, object);
   and_(TMP, TMP, CMPRES1);
   andi(CMPRES1, TMP, Immediate(kNewObjectAlignmentOffset));
   beq(CMPRES1, ZR, no_update);
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
+  ASSERT(!in_delay_slot_);
   ASSERT(object != value);
   sw(value, dest);
   Label done;
   if (can_value_be_smi) {
     StoreIntoObjectFilter(object, value, &done);
   } else {
     StoreIntoObjectFilterNoSmi(object, value, &done);
   }
   // A store buffer update is required.
   if (value != T0) {
@@ skipping 16 matching lines @@
   } else {
     addiu(SP, SP, Immediate(1 * kWordSize));
   }
   Bind(&done);
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          Register value) {
+  ASSERT(!in_delay_slot_);
   sw(value, dest);
 #if defined(DEBUG)
   Label done;
   StoreIntoObjectFilter(object, value, &done);
   Stop("Store buffer update is required");
   Bind(&done);
 #endif  // defined(DEBUG)
   // No store buffer update.
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          const Object& value) {
+  ASSERT(!in_delay_slot_);
   ASSERT(value.IsSmi() || value.InVMHeap() ||
          (value.IsOld() && value.IsNotTemporaryScopedHandle()));
   // No store buffer update.
   LoadObject(TMP, value);
   sw(TMP, dest);
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
   const intptr_t class_id_offset = Object::tags_offset() +
       RawObject::kClassIdTagPos / kBitsPerByte;
   lhu(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
+  ASSERT(!in_delay_slot_);
   ASSERT(result != class_id);
   lw(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
   lw(result, Address(result, table_offset_in_isolate));
   sll(TMP, class_id, 2);
   addu(result, result, TMP);
   lw(result, Address(result));
 }
 
 
 void Assembler::LoadClass(Register result, Register object) {
+  ASSERT(!in_delay_slot_);
   ASSERT(TMP != result);
   LoadClassId(TMP, object);
 
   lw(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
   lw(result, Address(result, table_offset_in_isolate));
   sll(TMP, TMP, 2);
   addu(result, result, TMP);
   lw(result, Address(result));
 }
 
 
 void Assembler::EnterFrame() {
+  ASSERT(!in_delay_slot_);
   addiu(SP, SP, Immediate(-2 * kWordSize));
   sw(RA, Address(SP, 1 * kWordSize));
   sw(FP, Address(SP, 0 * kWordSize));
   mov(FP, SP);
 }
 
 
 void Assembler::LeaveFrameAndReturn() {
+  ASSERT(!in_delay_slot_);
   mov(SP, FP);
   lw(RA, Address(SP, 1 * kWordSize));
   lw(FP, Address(SP, 0 * kWordSize));
   Ret();
   delay_slot()->addiu(SP, SP, Immediate(2 * kWordSize));
 }
 
 
 void Assembler::EnterStubFrame(bool load_pp) {
+  ASSERT(!in_delay_slot_);
   SetPrologueOffset();
   addiu(SP, SP, Immediate(-4 * kWordSize));
   sw(ZR, Address(SP, 3 * kWordSize));  // PC marker is 0 in stubs.
   sw(RA, Address(SP, 2 * kWordSize));
   sw(FP, Address(SP, 1 * kWordSize));
   sw(PP, Address(SP, 0 * kWordSize));
   addiu(FP, SP, Immediate(1 * kWordSize));
   if (load_pp) {
     // Setup pool pointer for this stub.
     LoadPoolPointer();
   }
 }
 
 
 void Assembler::LeaveStubFrame() {
+  ASSERT(!in_delay_slot_);
   addiu(SP, FP, Immediate(-1 * kWordSize));
   lw(RA, Address(SP, 2 * kWordSize));
   lw(FP, Address(SP, 1 * kWordSize));
   lw(PP, Address(SP, 0 * kWordSize));
   addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 
 void Assembler::LeaveStubFrameAndReturn(Register ra) {
+  ASSERT(!in_delay_slot_);
   addiu(SP, FP, Immediate(-1 * kWordSize));
   lw(RA, Address(SP, 2 * kWordSize));
   lw(FP, Address(SP, 1 * kWordSize));
   lw(PP, Address(SP, 0 * kWordSize));
   jr(ra);
   delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 
 void Assembler::UpdateAllocationStats(intptr_t cid,
                                       Register temp_reg,
                                       Heap::Space space) {
+  ASSERT(!in_delay_slot_);
   ASSERT(temp_reg != kNoRegister);
   ASSERT(temp_reg != TMP);
   ASSERT(cid > 0);
   Isolate* isolate = Isolate::Current();
   ClassTable* class_table = isolate->class_table();
   if (cid < kNumPredefinedCids) {
     const uword class_heap_stats_table_address =
         class_table->PredefinedClassHeapStatsTableAddress();
     const uword class_offset = cid * sizeof(ClassHeapStats);  // NOLINT
     const uword count_field_offset = (space == Heap::kNew) ?
@@ skipping 17 matching lines @@
     AddImmediate(TMP, 1);
     sw(TMP, Address(temp_reg, count_field_offset));
   }
 }
 
 
 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
                                               Register size_reg,
                                               Register temp_reg,
                                               Heap::Space space) {
+  ASSERT(!in_delay_slot_);
   ASSERT(temp_reg != kNoRegister);
   ASSERT(cid > 0);
   ASSERT(temp_reg != TMP);
   Isolate* isolate = Isolate::Current();
   ClassTable* class_table = isolate->class_table();
   if (cid < kNumPredefinedCids) {
     const uword class_heap_stats_table_address =
         class_table->PredefinedClassHeapStatsTableAddress();
     const uword class_offset = cid * sizeof(ClassHeapStats);  // NOLINT
     const uword count_field_offset = (space == Heap::kNew) ?
@@ skipping 30 matching lines @@
     addu(TMP, TMP, size_reg);
     sw(TMP, Address(temp_reg, size_field_offset));
   }
 }
 
 
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
                             Register instance_reg,
                             Register temp_reg) {
+  ASSERT(!in_delay_slot_);
   ASSERT(failure != NULL);
   if (FLAG_inline_alloc) {
     Heap* heap = Isolate::Current()->heap();
     const intptr_t instance_size = cls.instance_size();
     LoadImmediate(instance_reg, heap->TopAddress());
     lw(instance_reg, Address(instance_reg, 0));
     AddImmediate(instance_reg, instance_size);
 
     // instance_reg: potential next object start.
     LoadImmediate(TMP, heap->EndAddress());
@@ skipping 21 matching lines @@
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry,
                             intptr_t argument_count) {
   entry.Call(this, argument_count);
 }
 
 
 void Assembler::EnterDartFrame(intptr_t frame_size) {
+  ASSERT(!in_delay_slot_);
   const intptr_t offset = CodeSize();
 
   SetPrologueOffset();
 
   addiu(SP, SP, Immediate(-4 * kWordSize));
   sw(RA, Address(SP, 2 * kWordSize));
   sw(FP, Address(SP, 1 * kWordSize));
   sw(PP, Address(SP, 0 * kWordSize));
 
   GetNextPC(TMP);  // TMP gets the address of the next instruction.
@@ skipping 17 matching lines @@
   AddImmediate(SP, -frame_size);
 }
 
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate. We must also set up the pool pointer for the function.
 void Assembler::EnterOsrFrame(intptr_t extra_size) {
+  ASSERT(!in_delay_slot_);
   Comment("EnterOsrFrame");
 
   GetNextPC(TMP);  // TMP gets the address of the next instruction.
 
   // The runtime system assumes that the code marker address is
   // kEntryPointToPcMarkerOffset bytes from the entry.  Since there is no
   // code to set up the frame pointer, etc., the address needs to be adjusted.
   const intptr_t offset = kEntryPointToPcMarkerOffset - CodeSize();
   // Calculate the offset of the pool pointer from the PC.
   const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset() +
       CodeSize();
 
   // Adjust PC by the offset, and store it in the stack frame.
   AddImmediate(TMP, TMP, offset);
   sw(TMP, Address(FP, kPcMarkerSlotFromFp * kWordSize));
 
   // Restore return address.
   lw(RA, Address(FP, 1 * kWordSize));
 
   // Load the pool pointer. offset has already been subtracted from temp.
   lw(PP, Address(TMP, -object_pool_pc_dist - offset));
 
   // Reserve space for locals.
   AddImmediate(SP, -extra_size);
 }
 
 
 void Assembler::LeaveDartFrame() {
+  ASSERT(!in_delay_slot_);
   addiu(SP, FP, Immediate(-kWordSize));
 
   lw(RA, Address(SP, 2 * kWordSize));
   lw(FP, Address(SP, 1 * kWordSize));
   lw(PP, Address(SP, 0 * kWordSize));
 
   // Adjust SP for PC, RA, FP, PP pushed in EnterDartFrame.
   addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 
 void Assembler::LeaveDartFrameAndReturn() {
+  ASSERT(!in_delay_slot_);
   addiu(SP, FP, Immediate(-kWordSize));
 
   lw(RA, Address(SP, 2 * kWordSize));
   lw(FP, Address(SP, 1 * kWordSize));
   lw(PP, Address(SP, 0 * kWordSize));
 
   // Adjust SP for PC, RA, FP, PP pushed in EnterDartFrame, and return.
   Ret();
   delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 
 void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
+  ASSERT(!in_delay_slot_);
   // Reserve space for arguments and align frame before entering
   // the C++ world.
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
     LoadImmediate(TMP, ~(OS::ActivationFrameAlignment() - 1));
     and_(SP, SP, TMP);
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
+  ASSERT(!in_delay_slot_);
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
   SetPrologueOffset();
 
   TraceSimMsg("EnterCallRuntimeFrame");
 
   // Save volatile CPU and FPU registers on the stack:
@@ skipping 22 matching lines @@
   }
   sw(RA, Address(SP, 1 * kWordSize));
   sw(FP, Address(SP, 0 * kWordSize));
   mov(FP, SP);
 
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
+  ASSERT(!in_delay_slot_);
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
   TraceSimMsg("LeaveCallRuntimeFrame");
 
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
@@ skipping 84 matching lines @@
     Emit(reinterpret_cast<int32_t>(message));
     Bind(&msg);
     break_(Instr::kMsgMessageCode);
   }
 #endif
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS